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SN74LVC574APW PDF预览

SN74LVC574APW

更新时间： 2024-11-03 23:06:23
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
9页 144K
描述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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中文翻译

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SN74LVC574APW 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP20,.25针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：0.95
控制类型：ENABLE LOW计数方向：UNIDIRECTIONAL
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G20
JESD-609代码：e4长度：6.5 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大频率@ Nom-Sup：150000000 Hz最大I（ol）：0.024 A
湿度敏感等级：1位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP20,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TUBE峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：0.01 mA
Prop。Delay @ Nom-Sup：7 ns传播延迟（tpd）：21.6 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Bus Driver/Transceiver最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：4.4 mm
Base Number Matches：1

SN74LVC574APW 数据手册

 浏览型号SN74LVC574APW的Datasheet PDF文件第2页浏览型号SN74LVC574APW的Datasheet PDF文件第3页浏览型号SN74LVC574APW的Datasheet PDF文件第4页浏览型号SN74LVC574APW的Datasheet PDF文件第5页浏览型号SN74LVC574APW的Datasheet PDF文件第6页浏览型号SN74LVC574APW的Datasheet PDF文件第7页 
SN54LVC574A, SN74LVC574A  
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCAS301J – JANUARY 1993 – REVISED JULY 1998  
SN54LVC574A . . . J OR W PACKAGE  
SN74LVC574A . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
OE  
1D  
V
CC  
1Q  
1
2
3
4
5
6
7
8
9
10  
20  
19  
CC  
A
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
2D  
3D  
4D  
18 2Q  
17 3Q  
16 4Q  
= 3.3 V, T = 25°C  
A
Support Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
5D  
6D  
7D  
8D  
15  
14  
13  
12  
11  
5Q  
6Q  
7Q  
8Q  
CLK  
3.3-V V  
)
CC  
Power Off Disables Outputs, Permitting  
Live Insertion  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
GND  
SN54LVC574A . . . FK PACKAGE  
(TOP VIEW)  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW), and  
Ceramic Flat (W) Packages, Ceramic Chip  
Carriers (FK), and DIPs (J)  
3
2 1 20 19  
18  
2Q  
3Q  
4Q  
5Q  
6Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
17  
16  
15  
14  
description  
9 10 11 12 13  
The SN54LVC574A octal edge-triggered D-type  
flip-flop is designed for 2.7-V to 3.6-V V  
CC  
operation and the SN74LVC574A octal  
edge-triggered D-type flip-flop is designed for  
1.65-V to 3.6-V V  
operation.  
CC  
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively  
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers.  
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without interface or pullup components.  
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

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SN74LVC574APW 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC574APWLE TI

完全替代

 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LVC574APWT TI

类似代替

 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LVC574APWR TI

类似代替

 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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SN74LVC574APWLE TI

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SN74LVC574APWRE4 TI

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SN74LVC574APWRG4 TI

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SN74LVC574APWT TI

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SN74LVC574APWTE4 TI

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