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SN74LVC574ADBRG4

更新时间： 2024-01-28 09:11:26
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
30页 1169K
描述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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SN74LVC574ADBRG4 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：SSOP包装说明：SSOP-20
针数：20Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.06
Is Samacsys：N系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：7.2 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大频率@ Nom-Sup：150000000 Hz
最大I（ol）：0.024 A湿度敏感等级：1
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP20,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：3.3 V
Prop。Delay @ Nom-Sup：7 ns传播延迟（tpd）：21.6 ns
认证状态：Not Qualified座面最大高度：2 mm
子类别：FF/Latches最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：5.3 mm
Base Number Matches：1

SN74LVC574ADBRG4 数据手册

 浏览型号SN74LVC574ADBRG4的Datasheet PDF文件第2页浏览型号SN74LVC574ADBRG4的Datasheet PDF文件第3页浏览型号SN74LVC574ADBRG4的Datasheet PDF文件第4页浏览型号SN74LVC574ADBRG4的Datasheet PDF文件第5页浏览型号SN74LVC574ADBRG4的Datasheet PDF文件第6页浏览型号SN74LVC574ADBRG4的Datasheet PDF文件第7页 
SN54LVC574A, SN74LVC574A  
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCAS301R − JANUARY 1993 − REVISED MARCH 2005  
D
D
D
Operate From 1.65 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
D
Support Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
3.3-V V  
)
CC  
Specified From −40°C to 85°C,  
−40°C to 125°C, and −55°C to 125°C  
D
D
D
I
off  
Supports Partial-Power-Down Mode  
Operation  
D
Max t of 7 ns at 3.3 V  
pd  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
D
Typical V  
(Output Ground Bounce)  
OLP  
<0.8 V at V = 3.3 V, T = 25°C  
CC  
A
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
D
Typical V  
(Output V Undershoot)  
OHV  
OH  
>2 V at V = 3.3 V, T = 25°C  
CC  
A
− 1000-V Charged-Device Model (C101)  
SN54LVC574A . . . FK PACKAGE  
SN54LVC574A . . . J OR W PACKAGE  
SN74LVC574A . . . DB, DGV, DW, N, NS,  
OR PW PACKAGE  
SN74LVC574A . . . RGY PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
(TOP VIEW)  
1
20  
3
2 1 20 19  
18  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
VCC  
1Q  
18 2Q  
17 3Q  
16 4Q  
1
20  
19  
2Q  
3Q  
4Q  
5Q  
6Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
1Q  
18 2Q  
2
3
4
5
6
7
8
9
19  
2
17  
16  
15  
14  
3
17  
16  
15  
14  
13  
12  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
4
5
6
15  
14  
13  
12  
11  
5Q  
6Q  
7Q  
8Q  
CLK  
9 10 11 12 13  
7
8
9
10  
11  
10  
GND  
description/ordering information  
The SN54LVC574A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V V operation, and the  
CC  
SN74LVC574A octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V V operation.  
CC  
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively  
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers.  
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without interface or pullup components.  
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the  
off  
off  
outputs, preventing damaging current backflow through the device when it is powered down.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright © 2005, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
unless otherwise noted. On all other products, production  
testing of all parameters.  
processing does not necessarily include testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...30

中文翻译

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SN74LVC574ADBRG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC574ADBRE4 TI

完全替代

 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LVC574ADBR TI

类似代替

 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
74LCX574MSA FAIRCHILD

功能相似

 Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

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