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SN74LVC573DBR PDF预览

SN74LVC573DBR

更新时间： 2024-11-04 13:13:51
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
6页 83K
描述
LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, SSOP-20

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SN74LVC573DBR 技术参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP,针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.09Is Samacsys：N
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G20
长度：7.2 mm逻辑集成电路类型：BUS DRIVER
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
传播延迟（tpd）：10 ns认证状态：Not Qualified
座面最大高度：2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
宽度：5.3 mmBase Number Matches：1

SN74LVC573DBR 数据手册

 浏览型号SN74LVC573DBR的Datasheet PDF文件第2页浏览型号SN74LVC573DBR的Datasheet PDF文件第3页浏览型号SN74LVC573DBR的Datasheet PDF文件第4页浏览型号SN74LVC573DBR的Datasheet PDF文件第5页浏览型号SN74LVC573DBR的Datasheet PDF文件第6页 
SN74LVC573  
OCTAL TRANSPARENT D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
SCAS300A – JANUARY 1993 – REVISED NOVEMBER 1994  
DB, DW, OR PW PACKAGE  
(TOP VIEW)  
• EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
• Typical V  
(Output Ground Bounce)  
OLP  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
< 0.8 V at V  
= 3.3 V, T = 25°C  
CC  
A
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
• Typical V  
(Output V  
Undershoot)  
OHV  
OH  
> 2 V at V  
= 3.3 V, T = 25°C  
CC  
A
• Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages  
13 7Q  
12 8Q  
description  
11  
GND  
LE  
This octal transparent D-type latch is designed for  
2.7-V to 3.6-V V operation.  
CC  
The SN74LVC573 features 3-state outputs designed specifically for driving highly capacitive or relatively  
low-impedance loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports,  
bidirectional bus drivers, and working registers.  
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the  
Q outputs are latched at the logic levels at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without the need for interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
The SN74LVC573 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each latch)  
INPUTS  
OUTPUT  
Q
OE  
L
LE  
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
123456

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