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SN74LVC574 PDF预览

SN74LVC574

更新时间: 2024-09-29 05:16:59
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德州仪器 - TI 触发器输出元件
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5页 72K
描述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

SN74LVC574 数据手册

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SN74LVC574  
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
SCAS301 – JANUARY 1993 – REVISED MARCH 1994  
DB, DW, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
Typical V  
(Output Ground Bounce)  
OLP  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
< 0.8 V at V  
= 3.3 V, T = 25°C  
CC  
A
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
Typical V  
(Output V  
Undershoot)  
OHV  
OH  
> 2 V at V  
= 3.3 V, T = 25°C  
CC  
A
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages  
13 7Q  
12 8Q  
description  
11  
GND  
CLK  
This octal edge-triggered D-type flip-flop is  
designed for 2.7-V to 3.6-V V operation.  
CC  
The SN74LVC574 features 3-state outputs designed specifically for driving highly capacitive or relatively  
low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus  
drivers, and working registers.  
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels that were set up at  
the data (D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without need for interface or pullup components.  
The output-enable (OE) input does not affect the internal operations of the flip-flops. Old data can be retained  
or new data can be entered while the outputs are in the high-impedance state.  
The SN74LVC574 is characterized for operation from 40°C to 85°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
OE  
L
CLK  
D
H
L
H
L
L
L
L
X
X
X
Q
0
H
Z
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1994, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
7–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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