5秒后页面跳转
捷配首页

Datasheet > 暂无类别数据> SN74LVC3G17YEPR
SN74LVC3G17YEPR PDF预览

SN74LVC3G17YEPR

更新时间： 2024-11-15 22:23:35
品牌 Logo 应用领域
德州仪器 - TI 栅极逻辑集成电路
页数 文件大小 规格书
12页 259K
描述
TRIPLE SCHMITT TRIGGER BUFFER

阅读下载

中文翻译

获取价格

SN74LVC3G17YEPR 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：BGA包装说明：DSBGA-8
针数：8Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.57Is Samacsys：N
系列：LVC/LCX/ZJESD-30 代码：R-XBGA-B8
JESD-609代码：e0长度：1.9 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUFFER
最大I（ol）：0.024 A湿度敏感等级：1
功能数量：3输入次数：1
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：VFBGA封装等效代码：BGA8,2X4,20
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 VProp。Delay @ Nom-Sup：5.4 ns
传播延迟（tpd）：9.2 ns认证状态：Not Qualified
施密特触发器：YES座面最大高度：0.5 mm
子类别：Gates最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：0.5 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：0.9 mmBase Number Matches：1

SN74LVC3G17YEPR 数据手册

 浏览型号SN74LVC3G17YEPR的Datasheet PDF文件第2页浏览型号SN74LVC3G17YEPR的Datasheet PDF文件第3页浏览型号SN74LVC3G17YEPR的Datasheet PDF文件第4页浏览型号SN74LVC3G17YEPR的Datasheet PDF文件第5页浏览型号SN74LVC3G17YEPR的Datasheet PDF文件第6页浏览型号SN74LVC3G17YEPR的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢂ  
ꢈ
ꢊ
ꢋ
ꢌ
ꢍ
ꢄꢎ  
ꢀ
ꢆ
ꢏ
ꢐꢌ  
ꢊ
ꢊ
ꢑ
ꢊ
ꢋ
ꢌ
ꢈ
ꢎ
ꢋ
ꢒ
ꢓ
ꢔ
ꢔ
ꢎ
ꢋ
SCES470A − AUGUST 2003 − REVISED AUGUST 2003  
DCT OR DCU PACKAGE  
(TOP VIEW)  
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
D
D
D
D
D
D
Supports 5-V V  
Operation  
CC  
1A  
3Y  
2A  
V
CC  
1
2
3
4
8
7
6
5
Inputs Accept Voltages to 5.5 V  
1Y  
3A  
2Y  
Max t of 5.4 ns at 3.3 V  
pd  
Low Power Consumption, 10-µA Max I  
GND  
CC  
24-mA Output Drive at 3.3 V  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
= 3.3 V, T = 25°C  
OLP  
CC  
A
4 5  
3 6  
2 7  
1 8  
GND  
2A  
3Y  
2Y  
3A  
1Y  
D
D
D
D
Typical V  
(Output V  
Undershoot)  
OHV  
OH  
>2 V at V  
= 3.3 V, T = 25°C  
CC  
A
I
Supports Partial-Power-Down Mode  
off  
1A  
V
CC  
Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
This triple Schmitt-trigger buffer is designed for 1.65-V to 5.5-V V  
operation.  
CC  
The SN74LVC3G17 contains three buffers, and performs the Boolean function Y = A. The device functions as  
three independent buffers, but because of Schmitt action, it may have different input threshold levels for  
positive-going (V ) and negative-going (V ) signals.  
T+  
T−  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
A
PACKAGE  
‡
NanoStar− WCSP (DSBGA)  
0.23-mm Large Bump − YEP  
SN74LVC3G17YEPR  
SN74LVC3G17YZPR  
Tape and reel  
_ _ _C7_  
NanoFree− WCSP (DSBGA)  
0.23-mm Large Bump − YZP (Pb-free)  
−40°C to 85°C  
SSOP − DCT  
Tape and reel  
Tape and reel  
SN74LVC3G17DCTR  
SN74LVC3G17DCUR  
C17_ _ _  
C17_  
VSSOP − DCU  
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one  
following character to designate the assembly/test site. Pin  
1 identifier indicates solder-bump composition  
(1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
ꢍ
ꢍ
ꢋ
ꢕ
ꢧ
ꢖ
ꢢ
ꢓ
ꢆ
ꢠ
ꢊ
ꢡ
ꢌ
ꢛ
ꢕ
ꢙ
ꢁ
ꢚ
ꢖ
ꢗ
ꢊ
ꢗ
ꢘ
ꢙ
ꢣ
ꢚ
ꢛ
ꢡ
ꢜ
ꢝ
ꢞ
ꢞ
ꢟ
ꢟ
ꢘ
ꢘ
ꢛ
ꢛ
ꢙ
ꢙ
ꢘ
ꢠ
ꢠ
ꢤ
ꢡ
ꢢ
ꢜ
ꢜ
ꢣ
ꢣ
ꢙ
ꢟ
ꢞ
ꢝ
ꢠ
ꢠ
ꢛ
ꢚ
ꢤ
ꢊꢣ  
ꢢ
ꢥ
ꢠ
ꢦ
ꢘ
ꢡ
ꢞ
ꢠ
ꢟ
ꢘ
ꢟ
ꢛ
ꢜ
ꢙ
ꢢ
ꢧ
ꢞ
ꢙ
ꢟ
ꢟ
ꢣ
ꢠ
ꢨ
Copyright 2003, Texas Instruments Incorporated  
ꢜ
ꢛ
ꢡ
ꢟ
ꢛ
ꢜ
ꢝ
ꢟ
ꢛ
ꢠ
ꢤ
ꢘ
ꢚ
ꢘ
ꢡ
ꢣ
ꢜ
ꢟ
ꢩ
ꢟ
ꢣ
ꢜ
ꢛ
ꢚ
ꢪ
ꢞ
ꢌ
ꢙ
ꢝ
ꢣ
ꢠ
ꢟ
ꢞ
ꢙ
ꢧ
ꢞ
ꢜ
ꢧ
ꢫ
ꢞ
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
ꢜ
ꢜ
ꢞ
ꢙ
ꢟ
ꢬ
ꢨ
ꢍ
ꢜ
ꢛ
ꢧ
ꢢ
ꢡ
ꢟ
ꢘ
ꢛ
ꢙ
ꢤ
ꢜ
ꢛ
ꢡ
ꢣ
ꢠ
ꢠ
ꢘ
ꢙ
ꢭ
ꢧ
ꢛ
ꢣ
ꢠ
ꢙ
ꢛ
ꢟ
ꢙ
ꢣ
ꢡ
ꢣ
ꢠ
ꢠ
ꢞꢜ  
ꢘ
ꢦ
ꢬ
ꢘ
ꢙ
ꢡ
ꢦ
ꢢ
ꢧ
ꢣ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

中文翻译

下载PDF

SN74LVC3G17YEPR 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC3G17YZPR TI

类似代替

 TRIPLE SCHMITT TRIGGER BUFFER

与SN74LVC3G17YEPR相关器件

型号 品牌 获取价格 描述 数据表
SN74LVC3G17YZPR TI

获取价格

 		TRIPLE SCHMITT TRIGGER BUFFER
SN74LVC3G34 TI

获取价格

 		TRIPLE BUFFER GATE
SN74LVC3G34_07 TI

获取价格

 		TRIPLE BUFFER GATE
SN74LVC3G34_15 TI

获取价格

 		Triple Buffer Gate
SN74LVC3G34DCTR TI

获取价格

 		TRIPLE BUFFER GATE
SN74LVC3G34DCTRE4 TI

获取价格

 		TRIPLE BUFFER GATE
SN74LVC3G34DCTRG4 TI

获取价格

 		TRIPLE BUFFER GATE
SN74LVC3G34DCUR TI

获取价格

 		TRIPLE BUFFER GATE
SN74LVC3G34DCURE4 TI

获取价格

 		TRIPLE BUFFER GATE
SN74LVC3G34DCURG4 TI

获取价格

 		TRIPLE BUFFER GATE

与SN74LVC3G17YEPR相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证