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SN74LVC3G34DCTRG4 PDF预览

SN74LVC3G34DCTRG4

更新时间： 2024-02-16 05:12:26
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德州仪器 - TI /
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13页 526K
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TRIPLE BUFFER GATE

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SN74LVC3G34DCTRG4 数据手册

 浏览型号SN74LVC3G34DCTRG4的Datasheet PDF文件第2页浏览型号SN74LVC3G34DCTRG4的Datasheet PDF文件第3页浏览型号SN74LVC3G34DCTRG4的Datasheet PDF文件第4页浏览型号SN74LVC3G34DCTRG4的Datasheet PDF文件第5页浏览型号SN74LVC3G34DCTRG4的Datasheet PDF文件第6页浏览型号SN74LVC3G34DCTRG4的Datasheet PDF文件第7页 
SN74LVC3G34  
TRIPLE BUFFER GATE  
www.ti.com  
SCES366J–AUGUST 2001–REVISED FEBRUARY 2007  
FEATURES  
•
Available in the Texas Instruments  
NanoFree™ Package  
•
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
•
•
•
•
•
•
Supports 5-V VCC Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Inputs Accept Voltages to 5.5 V  
Max tpd of 4.1 ns at 3.3 V  
ESD Protection Exceeds JESD 22  
–
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
1000-V Charged-Device Model (C101)  
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
•
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
DCT PACKAGE  
(TOP VIEW)  
DCU PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(BOTTOM VIEW)  
4 5  
GND  
2A  
2Y  
3A  
VCC  
1Y  
3A  
2Y  
1
2
3
4
8
7
6
5
1A  
3Y  
VCC  
1Y  
3A  
2Y  
1
2
3
4
8
7
6
5
1A  
3Y  
3 6  
2 7  
1 8  
3Y  
1Y  
2A  
VCC  
1A  
GND  
2A  
GND  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This triple buffer gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC3G34 performs the Boolean  
function Y = A in positive logic.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
SSOP – DCT  
Reel of 3000  
SN74LVC3G34YZPR  
_ _ _C9_  
C34_ _ _  
Reel of 3000  
Reel of 3000  
Reel of 250  
SN74LVC3G34DCTR  
SN74LVC3G34DCUR  
SN74LVC3G34DCUT  
–40°C to 85°C  
VSSOP – DCU  
C34_  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2001–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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SN74LVC3G34DCTRG4 替代型号

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SN74LVC3G34DCTR TI

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 TRIPLE BUFFER GATE

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