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SN74LVC3G34YZPR PDF预览

SN74LVC3G34YZPR

更新时间: 2024-02-04 17:01:40
品牌 Logo 应用领域
德州仪器 - TI 逻辑集成电路
页数 文件大小 规格书
12页 317K
描述
TRIPLE BUFFER GATE

SN74LVC3G34YZPR 数据手册

 浏览型号SN74LVC3G34YZPR的Datasheet PDF文件第2页浏览型号SN74LVC3G34YZPR的Datasheet PDF文件第3页浏览型号SN74LVC3G34YZPR的Datasheet PDF文件第4页浏览型号SN74LVC3G34YZPR的Datasheet PDF文件第5页浏览型号SN74LVC3G34YZPR的Datasheet PDF文件第6页浏览型号SN74LVC3G34YZPR的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢇꢃ  
ꢉ ꢊꢋꢌ ꢄꢍ ꢎꢏꢐ ꢐꢍ ꢊ ꢈ ꢑꢉꢍ  
SCES366H − AUGUST 2001 − REVISED SEPTEMBER 2003  
DCT OR DCU PACKAGE  
(TOP VIEW)  
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
D
D
D
D
D
D
Supports 5-V V  
Operation  
CC  
1A  
3Y  
2A  
V
CC  
1
2
3
4
8
7
6
5
Inputs Accept Voltages to 5.5 V  
1Y  
3A  
2Y  
Max t of 4.1 ns at 3.3 V  
pd  
Low Power Consumption, 10-µA Max I  
GND  
CC  
24-mA Output Drive at 3.3 V  
YEA, YEP, YZA, OR YZP PACKAGE  
(BOTTOM VIEW)  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
= 3.3 V, T = 25°C  
OLP  
CC  
A
D
D
D
D
Typical V  
(Output V  
Undershoot)  
4 5  
3 6  
2 7  
1 8  
OHV  
OH  
GND  
2A  
3Y  
2Y  
3A  
1Y  
>2 V at V  
= 3.3 V, T = 25°C  
CC  
A
I
Supports Partial-Power-Down Mode  
off  
Operation  
1A  
V
CC  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
This triple buffer gate is designed for 1.65-V to 5.5-V V  
function Y = A in positive logic.  
operation. The SN74LVC3G34 performs the Boolean  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
NanoStar− WCSP (DSBGA)  
0.17-mm Small Bump − YEA  
SN74LVC3G34YEAR  
SN74LVC3G34YZAR  
SN74LVC3G34YEPR  
SN74LVC3G34YZPR  
NanoFree− WCSP (DSBGA)  
0.17-mm Small Bump − YZA (Pb-free)  
Reel of 3000  
_ _ _C9_  
NanoStar− WCSP (DSBGA)  
0.23-mm Large Bump − YEP  
−40°C to 85°C  
NanoFree− WCSP (DSBGA)  
0.23-mm Large Bump − YZP (Pb-free)  
SSOP − DCT  
Reel of 3000  
Reel of 3000  
SN74LVC3G34DCTR  
SN74LVC3G34DCUR  
C34_ _ _  
C34_  
VSSOP − DCU  
Reel of 250  
SN74LVC3G34DCUT  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,  
and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition  
(1 = SnPb, = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
ꢌꢊ ꢒ ꢓꢏ ꢆ ꢉꢋ ꢒ ꢁ ꢓ ꢑꢉꢑ ꢔꢕ ꢖ ꢗꢘ ꢙ ꢚꢛ ꢔꢗꢕ ꢔꢜ ꢝꢞ ꢘ ꢘ ꢟꢕꢛ ꢚꢜ ꢗꢖ ꢠꢞꢡ ꢢꢔꢝ ꢚꢛ ꢔꢗꢕ ꢣꢚ ꢛꢟ ꢤ  
ꢌꢘ ꢗ ꢣꢞꢝ ꢛ ꢜ ꢝ ꢗꢕ ꢖꢗ ꢘ ꢙ ꢛ ꢗ ꢜ ꢠꢟ ꢝ ꢔꢖ ꢔꢝꢚ ꢛꢔ ꢗꢕꢜ ꢠꢟ ꢘ ꢛꢥ ꢟ ꢛꢟ ꢘ ꢙꢜ ꢗꢖ ꢉꢟꢦ ꢚꢜ ꢋꢕꢜ ꢛꢘ ꢞꢙ ꢟꢕꢛ ꢜ  
ꢜ ꢛ ꢚ ꢕꢣ ꢚ ꢘꢣ ꢧ ꢚ ꢘꢘ ꢚ ꢕ ꢛꢨꢤ ꢌꢘ ꢗ ꢣꢞꢝ ꢛꢔꢗꢕ ꢠꢘ ꢗꢝ ꢟꢜ ꢜꢔ ꢕꢩ ꢣꢗꢟ ꢜ ꢕꢗꢛ ꢕꢟ ꢝꢟ ꢜꢜ ꢚꢘ ꢔꢢ ꢨ ꢔꢕꢝ ꢢꢞꢣ ꢟ  
ꢛ ꢟ ꢜ ꢛꢔ ꢕꢩ ꢗꢖ ꢚ ꢢꢢ ꢠꢚ ꢘ ꢚ ꢙ ꢟ ꢛ ꢟ ꢘ ꢜ ꢤ  
Copyright 2003, Texas Instruments Incorporated  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74LVC3G34YZPR 替代型号

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