Datasheet > SN74LVC2G74_09

SN74LVC2G74_09

更新时间： 2024-11-19 11:54:51

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
16页	540K
描述
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

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SN74LVC2G74_09 数据手册

SN74LVC2G74

SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH CLEAR AND PRESET

www.ti.com

SCES203M–APRIL 1999–REVISED FEBRUARY 2007

FEATURES

•

Available in the Texas Instruments

NanoFree™ Package

•

Typical V_OHV(Output V_OHUndershoot)

>2 V at V_CC= 3.3 V, T_A= 25°C

•

Supports 5-V V_CCOperation

I_offSupports Partial-Power-Down Mode

Operation

Inputs Accept Voltages to 5.5 V

Max t_pdof 5.9 ns at 3.3 V

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

Low Power Consumption, 10-µA Max I_CC

±24-mA Output Drive at 3.3 V

ESD Protection Exceeds JESD 22

–

2000-V Human-Body Model (A114-A)

200-V Machine Model (A115-A)

Typical V_OLP(Output Ground Bounce)

<0.8 V at V_CC= 3.3 V, T_A= 25°C

1000-V Charged-Device Model (C101)

DCT PACKAGE

(TOP VIEW)

DCU PACKAGE

(TOP VIEW)

YZP PACKAGE

(BOTTOM VIEW)

4 5

V_CC

PRE

CLR

GND

CLK

V_CC

CLK

3 6

2 7

1 8

CLR

PRE

V_CC

PRE

CLR

CLK

GND

See mechanical drawings for dimensions.

DESCRIPTION/ORDERING INFORMATION

This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V V_CCoperation.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the

other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time

requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs

at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,

data at the D input can be changed without affecting the levels at the outputs.

This device is fully specified for partial-power-down applications using I_off. The I_offcircuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾

ORDERABLE PART NUMBER TOP-SIDE MARKING⁽²⁾

NanoFree™ – WCSP (DSBGA)

0.23-mm Large Bump – YZP (Pb-free)

SSOP – DCT

Reel of 3000

SN74LVC2G74YZPR

_ _ _CP_

C74_ _ _

Reel of 3000

Reel of 250

SN74LVC2G74DCTR

SN74LVC2G74DCUR

SN74LVC2G74DCUT

–40°C to 85°C

VSSOP – DCU

C74_

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.

DCU: The actual top-side marking has one additional character that designates the assembly/test site.

YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoFree is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...16

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与SN74LVC2G74_09相关器件

型号	品牌	获取价格	描述	数据表
SN74LVC2G74DCT3	TI	获取价格	具有清零和预置端的单路正边沿触发式 D 型触发器 \| DCT \| 8 \| -40 to 1
SN74LVC2G74DCTR	TI	获取价格	SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC2G74DCTRE4	TI	获取价格	SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC2G74DCTRE6	TI	获取价格	具有清零和预置端的单路正边沿触发式 D 型触发器 \| DCT \| 8 \| -40 to 1
SN74LVC2G74DCTRG4	TI	获取价格	SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC2G74DCU	TI	获取价格	LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8, PLASTI
SN74LVC2G74DCUR	TI	获取价格	SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC2G74DCURE4	TI	获取价格	SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC2G74DCURG4	TI	获取价格	SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC2G74DCUT	TI	获取价格	SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

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