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SN74LV74ADGV PDF预览

SN74LV74ADGV

更新时间： 2024-11-14 23:03:19
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 159K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

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SN74LV74ADGV 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：TSSOP, TSSOP14,.25,16针数：14
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.58系列：LV/LV-A/LVX/H
JESD-30 代码：R-PDSO-G14长度：4.4 mm
逻辑集成电路类型：D FLIP-FLOP位数：1
功能数量：2端子数量：14
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP14,.25,16
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd）：23 ns认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.4 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：3.6 mm
最小 fmax：110 MHzBase Number Matches：1

SN74LV74ADGV 数据手册

 浏览型号SN74LV74ADGV的Datasheet PDF文件第2页浏览型号SN74LV74ADGV的Datasheet PDF文件第3页浏览型号SN74LV74ADGV的Datasheet PDF文件第4页浏览型号SN74LV74ADGV的Datasheet PDF文件第5页浏览型号SN74LV74ADGV的Datasheet PDF文件第6页浏览型号SN74LV74ADGV的Datasheet PDF文件第7页 
SN54LV74A, SN74LV74A  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
SCLS381D – AUGUST 1997 – REVISED JUNE 1998  
SN54LV74A . . . J OR W PACKAGE  
SN74LV74A . . . D, DB, DGV, NS, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
Typical V (Output Ground Bounce)  
OLP  
< 0.8 V at V , T = 25°C  
CC  
A
1CLR  
1D  
V
CC  
2CLR  
2D  
1
2
3
4
5
6
7
14  
13  
12  
11  
Typical V  
> 2 V at V , T = 25°C  
(Output V  
Undershoot)  
OHV  
CC  
OH  
1CLK  
1PRE  
1Q  
A
2CLK  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
10 2PRE  
9
8
1Q  
2Q  
2Q  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
GND  
SN54LV74A . . . FK PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D, NS), Shrink Small-Outline  
(DB), Thin Very Small-Outline (DGV), and  
Thin Shrink Small-Outline (PW) Packages,  
Ceramic Flat (W) Packages, Chip Carriers  
(FK), and DIPs (J)  
3
2
1
20 19  
18  
2D  
1CLK  
NC  
4
5
6
7
8
NC  
17  
16  
description  
2CLK  
1PRE  
NC  
15 NC  
14  
These dual positive-edge-triggered D-type  
flip-flops are designed for 2-V to 5.5-V V  
operation.  
2PRE  
1Q  
CC  
9 10 11 12 13  
A low level at the preset (PRE) or clear (CLR)  
inputs sets or resets the outputs, regardless of the  
levels of the other inputs. When PRE and CLR are  
inactive (high), data at the data (D) inputs meeting  
the setup-time requirements is transferred to the  
outputs on the positive-going edge of the clock  
pulse. Clock triggering occurs at a voltage level  
and is not directly related to the rise time of the  
clock pulse. Following the hold-time interval, data  
attheDinputcanbechangedwithoutaffectingthe  
levels at the outputs.  
NC – No internal connection  
The SN54LV74A is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74LV74A is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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