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SN74LV374A-Q1 PDF预览

SN74LV374A-Q1

更新时间： 2024-09-10 12:22:31
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德州仪器 - TI 触发器输出元件
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11页 199K
描述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

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SN74LV374A-Q1 数据手册

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SN74LV374A-Q1  
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
SCLS468C − FEBRUARY 2003 − REVISED JANUARY 2008  
PW PACKAGE  
(TOP VIEW)  
D
D
Qualified for Automotive Applications  
Typical V (Output Ground Bounce)  
OLP  
<0.8 V at V = 3.3 V, T = 25°C  
CC  
A
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
VCC  
1
2
3
4
5
6
7
8
9
10  
20  
D
D
D
D
Typical V  
(Output V Undershoot)  
19 8Q  
18 8D  
OHV  
OH  
>2.3 V at V = 3.3 V, T = 25°C  
CC  
A
17  
16  
15  
14  
13  
12  
11  
7D  
7Q  
6Q  
6D  
5D  
5Q  
CLK  
Supports Mixed-Mode Voltage Operation on  
All Ports  
I
off  
Supports Partial-Power-Down Mode  
Operation  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
GND  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
The SN74LV374A is an octal edge-triggered D-type flip-flop designed for 2-V to 5.5-V V operation.  
CC  
This device features 3-state outputs designed specifically for driving highly capacitive or relatively  
low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus  
drivers, and working registers.  
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D)  
inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the  
bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines  
without need for interface or pullup components.  
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION†  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
T
A
PACKAGE  
−40°C to 105°C  
TSSOP − PW Tape and reel  
SN74LV374ATPWRQ1  
LV374ATQ  
†
‡
For the most current package and ordering information, see the Package Option Addendum at the end of this  
document, or see the TI web site at http://www.ti.com.  
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright © 2008, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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SN74LV374A-Q1 替代型号

型号 品牌 替代类型 描述 数据表
SN74LV374A-EP TI

功能相似

 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LV374A TI

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