5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SN74LV374ATDWG4
SN74LV374ATDWG4 PDF预览

SN74LV374ATDWG4

更新时间： 2024-09-10 11:58:27
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
21页 874K
描述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

SN74LV374ATDWG4 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：PLASTIC, SOIC-20针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.29Is Samacsys：N
系列：LV/LV-A/LVX/HJESD-30 代码：R-PDSO-G20
JESD-609代码：e4长度：12.8 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大频率@ Nom-Sup：50000000 Hz最大I（ol）：0.008 A
湿度敏感等级：1位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP20,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TUBE峰值回流温度（摄氏度）：260
电源：3.3 VProp。Delay @ Nom-Sup：18.5 ns
传播延迟（tpd）：23 ns认证状态：Not Qualified
座面最大高度：2.65 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：7.5 mmBase Number Matches：1

SN74LV374ATDWG4 数据手册

 浏览型号SN74LV374ATDWG4的Datasheet PDF文件第2页浏览型号SN74LV374ATDWG4的Datasheet PDF文件第3页浏览型号SN74LV374ATDWG4的Datasheet PDF文件第4页浏览型号SN74LV374ATDWG4的Datasheet PDF文件第5页浏览型号SN74LV374ATDWG4的Datasheet PDF文件第6页浏览型号SN74LV374ATDWG4的Datasheet PDF文件第7页 
SN74LV374AT  
www.ti.com  
SCES632 –JUNE 2010  
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS  
Check for Samples: SN74LV374AT  
1
FEATURES  
•
•
•
•
Inputs Are TTL-Voltage Compatible  
•
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
4.5-V to 5.5-V VCC Operation  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Typical tpd of 4.9 ns at 5 V  
Typical VOLP (Output Ground Bounce) <0.8 V  
at VCC = 5 V, TA = 25°C  
ESD Protection Exceeds JESD 22  
–
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
•
•
Typical VOHV (Output VOH Undershoot) >2.3 V  
at VCC = 5 V, TA = 25°C  
1000-V Charged-Device Model (C101)  
Support Mixed-Mode Voltage Operation on All  
Ports  
DB, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
RGY PACKAGE  
(TOP VIEW)  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
VCC  
8Q  
8D  
7D  
7Q  
6Q  
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
1
20  
19  
18  
17  
16  
15  
14  
13  
12  
2
3
4
5
6
7
8
9
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
14 6D  
13 5D  
12 5Q  
11 CLK  
GND 10  
10  
11  
DESCRIPTION  
The SN74LV374AT is an octal edge-triggered D-type flip-flop. This device features 3-state outputs designed  
specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for  
implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.  
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D)  
inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or  
low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines  
without need for interface or pullup components.  
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2010, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...21

中文翻译

下载PDF

SN74LV374ATDWG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74LV374ATDWR TI

完全替代

 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

与SN74LV374ATDWG4相关器件

型号 品牌 获取价格 描述 数据表
SN74LV374ATDWR TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LV374ATDWRG4 TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LV374ATNS TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LV374ATNSG4 TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LV374ATNSR TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LV374ATNSRG4 TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LV374ATPW TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LV374ATPWE4 TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LV374ATPWG4 TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LV374ATPWR TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

与SN74LV374ATDWG4相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证