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SCLS500A − MAY 2003 − REVISED MAY 2004
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
D
I
Supports Partial-Power-Down Mode
off
Operation
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
D
D
D
D
D
D
D
Extended Temperature Performance of
−40°C to 105°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
− 1000-V Charged-Device Model (C101)
PW PACKAGE
(TOP VIEW)
Enhanced Product-Change Notification
†
Qualification Pedigree
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
1
2
3
4
5
6
7
8
9
20
Typical V
<0.8 V at V
(Output Ground Bounce)
= 3.3 V, T = 25°C
OLP
CC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 CLK
A
Typical V
>2.3 V at V
(Output V
= 3.3 V, T = 25°C
Undershoot)
OHV
CC
OH
A
Supports Mixed-Mode Voltage Operation on
All Ports
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
GND 10
description/ordering information
The SN74LV374A is an octal edge-triggered D-type flip-flop designed for 2-V to 5.5-V V
operation.
CC
This device features 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D)
inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
PACKAGE
T
A
−40°C to 105°C
TSSOP − PW Tape and reel SN74LV374ATPWREP LV374AEP
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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1
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