SN74LV374AT

更新时间： 2024-09-10 11:58:27

品牌	Logo	应用领域
德州仪器 - TI		触发器输出元件
页数	文件大小	规格书
21页	874K
描述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

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SN74LV374AT 数据手册

SN74LV374AT

www.ti.com

SCES632 –JUNE 2010

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

Check for Samples: SN74LV374AT

FEATURES

•

Inputs Are TTL-Voltage Compatible

•

I_offSupports Partial-Power-Down Mode

Operation

4.5-V to 5.5-V V_CCOperation

Latch-Up Performance Exceeds 250 mA Per

JESD 17

Typical t_pdof 4.9 ns at 5 V

Typical V_OLP(Output Ground Bounce) <0.8 V

at V_CC= 5 V, T_A= 25°C

ESD Protection Exceeds JESD 22

–

2000-V Human-Body Model (A114-A)

200-V Machine Model (A115-A)

•

Typical V_OHV(Output V_OHUndershoot) >2.3 V

at V_CC= 5 V, T_A= 25°C

1000-V Charged-Device Model (C101)

Support Mixed-Mode Voltage Operation on All

Ports

DB, DW, NS, OR PW PACKAGE

(TOP VIEW)

RGY PACKAGE

(TOP VIEW)

V_CC

14 6D

13 5D

12 5Q

11 CLK

GND 10

DESCRIPTION

The SN74LV374AT is an octal edge-triggered D-type flip-flop. This device features 3-state outputs designed

specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for

implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D)

inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or

low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus

lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines

without need for interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CCthrough a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_offcircuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...21

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与SN74LV374AT相关器件

型号	品牌	获取价格	描述	数据表
SN74LV374ATDB	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LV374ATDBG4	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LV374ATDBR	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LV374ATDBRG4	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LV374ATDW	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LV374ATDWG4	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LV374ATDWR	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LV374ATDWRG4	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LV374ATNS	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LV374ATNSG4	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

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