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SN74HC166A-EP PDF预览

SN74HC166A-EP

更新时间： 2024-09-15 12:22:03
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器
页数 文件大小 规格书
13页 384K
描述
8-BIT PARALLEL-LOAD SHIFT REGISTER

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中文翻译

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SN74HC166A-EP 数据手册

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SCLS559 − JANUARY 2004  
D
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
D
D
D
D
4-mA Output Drive at 5 V  
Low Input Current of 1 µA Max  
Synchronous Load  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
Direct Overriding Clear  
Parallel-to-Serial Conversion  
D
D
D
D
D
D
Enhanced Product-Change Notification  
†
Qualification Pedigree  
D OR PW PACKAGE  
(TOP VIEW)  
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive Up To 10 LSTTL Loads  
SER  
V
CC  
SH/LD  
H
1
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16  
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10  
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Low Power Consumption, 80-µA Max I  
A
CC  
B
C
Typical t = 13 ns  
pd  
†
Q
H
G
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
D
CLK INH  
CLK  
F
E
GND  
CLR  
description/ordering information  
This parallel-in or serial-in, serial-out register features gated clock (CLK, CLK INH) inputs and an overriding  
clear (CLR) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD) input. When high,  
SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock  
(CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on  
the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the  
low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a  
clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low  
enables the other clock input. This allows the system clock to be free running, and the register can be stopped  
on command with the other clock input. CLK INH should be changed to the high level only when CLK is high.  
CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
PACKAGE  
T
A
SOIC − D  
Tape and reel  
Tape and reel  
SN74HC166AIDREP  
SN74HC166AIPWREP  
SHC166IEP  
SHC166IEP  
−40°C to 85°C  
§
TSSOP − PW  
‡
§
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Product Preview  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

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