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SN74HC166AIDRQ1 PDF预览

SN74HC166AIDRQ1

更新时间: 2024-11-26 11:58:23
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
16页 620K
描述
8-BIT PARALLEL-LOAD SHIFT REGISTER

SN74HC166AIDRQ1 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOIC-16针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:0.7Is Samacsys:N
其他特性:CLOCK INHIBIT计数方向:RIGHT
系列:HC/UHJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:PARALLEL IN SERIAL OUT
最大频率@ Nom-Sup:25000000 Hz最大I(ol):0.004 A
湿度敏感等级:1位数:8
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TR峰值回流温度(摄氏度):260
电源:2/6 V最大电源电流(ICC):0.08 mA
Prop。Delay @ Nom-Sup:32 ns传播延迟(tpd):190 ns
认证状态:Not Qualified施密特触发器:No
筛选级别:AEC-Q100座面最大高度:1.75 mm
子类别:Shift Registers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:3.91 mm
最小 fmax:29 MHzBase Number Matches:1

SN74HC166AIDRQ1 数据手册

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ꢀꢁꢂ ꢃ ꢄ ꢅꢆ ꢇꢇ ꢈꢉ ꢊ ꢆ  
ꢋ ꢉꢌꢍ ꢎ ꢏꢈꢐꢈ ꢑꢑ ꢒꢑ ꢉꢑ ꢓ ꢈꢔ ꢀꢄ ꢍꢕ ꢎ ꢐꢒ ꢖ ꢍꢀ ꢎꢒ ꢐ  
SCLS538A − AUGUST 2003 − REVISED APRIL 2008  
D
D
Qualified for Automotive Applications  
D
D
D
D
Low Input Current of 1 µA Max  
Synchronous Load  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
Direct Overriding Clear  
Parallel-to-Serial Conversion  
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive Up To 10 LSTTL Loads  
D OR PW PACKAGE  
(TOP VIEW)  
Low Power Consumption, 80-µA Max I  
Typical t = 13 ns  
pd  
4-mA Output Drive at 5 V  
CC  
SER  
V
CC  
SH/LD  
H
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
A
B
C
Q
H
G
D
description/ordering information  
CLK INH  
CLK  
F
This parallel-in or serial-in, serial-out register  
features gated clock (CLK, CLK INH) inputs and an  
overriding clear (CLR) input. The parallel-in or  
serial-in modes are established by the shift/load  
E
GND  
CLR  
(SH/LD) input. When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial  
shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and  
synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited.  
Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting  
one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits  
clocking; holding either low enables the other clock input. This allows the system clock to be free running, and  
the register can be stopped on command with the other clock input. CLK INH should be changed to the high  
level only when CLK is high. CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.  
{
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
SOIC − D  
Tape and reel  
Tape and reel  
SN74HC166AIDRQ1  
SN74HC166AIPWRQ1  
HC166AI  
HC166AI  
−40°C to 85°C  
TSSOP − PW  
For the most current package and ordering information, see the Package Option Addendum at the end of this  
document, or see the TI web site at http://www.ti.com.  
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢎꢣ  
Copyright 2008, Texas Instruments Incorporated  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74HC166AIDRQ1 替代型号

型号 品牌 替代类型 描述 数据表
SN74HC166AIDREP TI

完全替代

8-BIT PARALLEL-LOAD SHIFT REGISTER
V62/04690-01XE TI

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8-BIT PARALLEL-LOAD SHIFT REGISTER
SN74HC166DR TI

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