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SN74HC166A-Q1 PDF预览

SN74HC166A-Q1

更新时间： 2024-11-06 11:07:07
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器
页数 文件大小 规格书
16页 620K
描述
汽车类 8 位并联负载移位寄存器

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中文翻译

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SN74HC166A-Q1 数据手册

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SCLS538A − AUGUST 2003 − REVISED APRIL 2008  
D
D
Qualified for Automotive Applications  
D
D
D
D
Low Input Current of 1 µA Max  
Synchronous Load  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
Direct Overriding Clear  
Parallel-to-Serial Conversion  
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive Up To 10 LSTTL Loads  
D OR PW PACKAGE  
(TOP VIEW)  
Low Power Consumption, 80-µA Max I  
Typical t = 13 ns  
pd  
4-mA Output Drive at 5 V  
CC  
SER  
V
CC  
SH/LD  
H
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description/ordering information  
CLK INH  
CLK  
F
This parallel-in or serial-in, serial-out register  
features gated clock (CLK, CLK INH) inputs and an  
overriding clear (CLR) input. The parallel-in or  
serial-in modes are established by the shift/load  
E
GND  
CLR  
(SH/LD) input. When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial  
shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and  
synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited.  
Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting  
one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits  
clocking; holding either low enables the other clock input. This allows the system clock to be free running, and  
the register can be stopped on command with the other clock input. CLK INH should be changed to the high  
level only when CLK is high. CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.  
{
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
PACKAGE  
T
A
SOIC − D  
Tape and reel  
Tape and reel  
SN74HC166AIDRQ1  
SN74HC166AIPWRQ1  
HC166AI  
HC166AI  
−40°C to 85°C  
TSSOP − PW  
†
‡
For the most current package and ordering information, see the Package Option Addendum at the end of this  
document, or see the TI web site at http://www.ti.com.  
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2008, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...16

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