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SN74AUP1G58DRLR

更新时间： 2024-11-26 22:29:51
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德州仪器 - TI /
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18页 426K
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LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE

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SN74AUP1G58DRLR 数据手册

 浏览型号SN74AUP1G58DRLR的Datasheet PDF文件第2页浏览型号SN74AUP1G58DRLR的Datasheet PDF文件第3页浏览型号SN74AUP1G58DRLR的Datasheet PDF文件第4页浏览型号SN74AUP1G58DRLR的Datasheet PDF文件第5页浏览型号SN74AUP1G58DRLR的Datasheet PDF文件第6页浏览型号SN74AUP1G58DRLR的Datasheet PDF文件第7页 
SN74AUP1G58  
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE  
www.ti.com  
SCES504D–NOVEMBER 2003–REVISED JUNE 2005  
FEATURES  
•
•
Optimized for 3.3-V Operation  
•
•
•
Available in the Texas Instruments  
NanoStar™ and NanoFree™ Packages  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
Low Static-Power Consumption  
(ICC = 0.9 µA Max)  
•
•
•
tpd = 5.5 ns Max at 3.3 V  
Suitable for Point-to-Point Applications  
Low Dynamic-Power Consumption  
(Cpd = 4.6 pF Typ at 3.3 V)  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
•
Low Input Capacitance (Ci = 1.5 pF Typ)  
•
ESD Performance Tested Per JESD 22  
Low Noise - Overshoot and Undershoot <10%  
of VCC  
– 2000-V Human-Body Model  
(A114-B, Class II)  
•
Ioff Supports Partial-Power-Down Mode  
Operation  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
•
•
Includes Schmitt-Trigger Inputs  
•
ESD Protection Exceeds ±5000 V With  
Human-Body Model  
Wide Operating VCC Range of 0.8 V to 3.6 V  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
3
4
Y
V
In0  
GND  
In1  
1
2
3
6
5
4
In1  
GND  
In0  
In2  
In1  
GND  
In0  
In2  
1
2
3
6
5
4
1
2
3
6
In1  
GND  
In0  
In2  
V
2 5  
CC  
V
Y
CC  
V
Y
CC  
1
6
In2  
5
4
CC  
Y
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable  
applications. This family ensures a very low static and dynamic power consumption across the entire VCC range  
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity,  
which produces very low undershoot and overshoot characteristics.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
NanoStar™ – WCSP (DSBGA)  
0.23-mm Large Bump – YEP  
Tape and reel  
Tape and reel  
SN74AUP1G58YEPR  
_ _ _HJ_  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
SN74AUP1G58YZPR  
–40°C to 85°C  
SOT (SOT-23) – DBV  
SOT (SC-70) – DCK  
SOT (SOT-553) – DRL  
Tape and reel  
Tape and reel  
Reel of 4000  
SN74AUP1G58DBVR  
SN74AUP1G58DCKR  
SN74AUP1G58DRLR  
H58_  
HJ_  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...18

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SN74AUP1G58DRLR 替代型号

型号 品牌 替代类型 描述 数据表
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