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SN74AUP1G74

更新时间： 2024-11-16 05:24:51
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德州仪器 - TI 触发器
页数 文件大小 规格书
17页 259K
描述
LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

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SN74AUP1G74 数据手册

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SN74AUP1G74  
LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH CLEAR AND PRESET  
www.ti.com  
SCES644A–MARCH 2006–REVISED SEPTEMBER 2006  
FEATURES  
•
•
•
Available in the Texas Instruments  
NanoStar™ and NanoFree™ Packages  
•
•
Optimized for 3.3-V Operation  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
Low Static-Power Consumption:  
ICC = 0.9 µA Max  
•
•
•
tpd = 4.3 ns Max at 3.3 V  
Low Dynamic-Power Consumption:  
Cpd = 4.3 pF Typ at 3.3 V  
Suitable for Point-to-Point Applications  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
•
Low Input Capacitance: Ci = 1.5 pF Typ  
Low Noise – Overshoot and Undershoot  
<10% of VCC  
•
ESD Performance Tested Per JESD 22  
– 2000-V Human-Body Model  
(A114-B, Class II)  
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
– 200-V Machine Model (A115-A)  
Schmitt-Trigger Action Allows Slow Input  
Transition and Better Switching Noise  
Immunity at the Input (Vhys = 250 mV Typ at  
3.3 V)  
– 1000-V Charged-Device Model (C101)  
•
ESD Protection Exceeds ±5000 V With  
Human-Body Model  
•
Wide Operating VCC Range of 0.8 V to 3.6 V  
DCT PACKAGE  
(TOP VIEW)  
DCU PACKAGE  
(TOP VIEW)  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
4 5  
Q
CLR  
PRE  
GND  
Q
D
CLK  
CLK  
D
Q
GND  
V
CC  
1
2
3
4
8
7
6
5
1
2
8
7
CLK  
D
V
CC  
3 6  
PRE  
CLR  
Q
2
7
PRE  
1 8  
V
CC  
3
4
6
5
Q
CLR  
Q
GND  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable  
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range  
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal  
integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
NanoStar™ – WCSP (DSBGA)  
0.23-mm Large Bump – YEP  
Reel of 3000  
Reel of 3000  
SN74AUP1G74YEPR  
_ _ _HS_  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
SN74AUP1G74YZPR  
–40°C to 85°C  
SSOP – DCT  
Reel of 3000  
Reel of 3000  
SN74AUP1G74DCTR  
SN74AUP1G74DCUR  
H74_ _ _  
H74_  
VSSOP – DCU  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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