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SN74AUP1G79DPWR

更新时间： 2024-11-17 11:07:11
品牌 Logo 应用领域
德州仪器 - TI 逻辑集成电路触发器锁存器
页数 文件大小 规格书
15页 265K
描述
低功耗单路正边沿触发式 D 型触发器 | DPW | 5 | -40 to 85

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中文翻译

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SN74AUP1G79DPWR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：HVBCC,
Reach Compliance Code：compliantECCN代码：EAR99
Factory Lead Time：6 weeks风险等级：1.55
系列：AUP/ULP/VJESD-30 代码：S-PBCC-B5
JESD-609代码：e4长度：0.8 mm
逻辑集成电路类型：D FLIP-FLOP最大I（ol）：0.004 A
湿度敏感等级：1位数：1
功能数量：1端子数量：5
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：HVBCC封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：NOT SPECIFIED
最大电源电流（ICC）：0.0009 mA传播延迟（tpd）：24 ns
座面最大高度：0.4 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：0.8 V标称供电电压 (Vsup)：1.2 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：BUTT端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：0.8 mm最小 fmax：260 MHz

SN74AUP1G79DPWR 数据手册

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SCES592A − JULY 2004 − REVISED SEPTEMBER 2005  
D
D
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
Low Static-Power Consumption;  
D
D
D
D
D
D
Wide Operating V  
Range of 0.8 V to 3.6 V  
CC  
Optimized for 3.3-V Operation  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
I
= 0.9 µA Max  
CC  
Low Dynamic-Power Consumption;  
= 3 pF Typ at 3.3 V  
t
= 3.6 ns Max at 3.3 V  
pd  
C
pd  
Suitable for Point-to-Point Applications  
D
Low Input Capacitance; C = 1.5 pF Typ  
i
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
D
Low Noise − Overshoot and Undershoot  
<10% of V  
CC  
D
ESD Performance Tested Per JESD 22  
− 2000-V Human-Body Model  
(A114-B, Class II)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
D
D
I
Supports Partial-Power-Down Mode  
off  
Operation  
Input Hysteresis Allows Slow Input  
Transition and Better Switching Noise  
Immunity at the Input  
D
ESD Protection Exceeds 5000 V With  
Human-Body Model  
(V  
= 250 mV Typ at 3.3 V)  
hys  
DBV OR DCK PACKAGE  
(TOP VIEW)  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
3 4  
2
GND  
CLK  
D
Q
V
1
2
3
5
4
D
CLK  
GND  
V
CC  
1 5  
Q
CC  
description/ordering information  
The AUP family is TI’s premier solution to the industry’s low power needs in battery-powered portable  
applications. This family ensures a very low static and dynamic power consumption across the entire V range  
CC  
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see  
Figures 1 and 2).  
Static-Power Consumption  
Dynamic-Power Consumption  
(pF)  
Switching Characteristics  
†
(µA)  
at 25 MHz  
3.5  
3
100%  
100%  
80%  
60%  
80%  
2.5  
2
Input  
Output  
60%  
40%  
3.3-V  
3.3-V  
†  
Logic  
1.5  
1
†
Logic  
40%  
0.5  
0
20%  
0%  
20%  
0%  
AUP  
AUP  
−0.5  
10  
15 20  
Time − ns  
0
5
25  
35 40 45  
30  
†
Single, dual, and triple gates  
†
AUP1G08 data at C = 15 pF  
L
Figure 2. Excellent Signal Integrity  
Figure 1. AUP − The Lowest-Power Family  
This is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time  
requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock  
triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the  
hold-time interval, data at the D input can be changed without affecting the levels at the outputs.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
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Copyright 2005, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

中文翻译

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