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SN74AUP1G80_08

更新时间： 2024-02-18 15:12:20
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德州仪器 - TI 触发器
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17页 501K
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LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

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SN74AUP1G80_08 数据手册

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SN74AUP1G80  
LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
www.ti.com  
SCES593B–JULY 2004–REVISED JULY 2005  
FEATURES  
•
•
•
Available in the Texas Instruments  
NanoStar™ and NanoFree™ Packages  
•
•
•
Wide Operating VCC Range of 0.8 V to 3.6 V  
Optimized for 3.3-V Operation  
Low Static-Power Consumption  
(ICC = 0.9 µA Max)  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
Low Dynamic-Power Consumption  
(Cpd = 4.3 pF Typ at 3.3 V)  
•
•
•
tpd = 4.3 ns Max at 3.3 V  
Suitable for Point-to-Point Applications  
•
•
Low Input Capacitance (Ci = 1.5 pF Typ)  
Latch-Up Performance Exceeds 100 mA  
Per JESD 78, Class II  
Low Noise – Overshoot and Undershoot  
<10% of VCC  
•
ESD Performance Tested Per JESD 22  
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
– 2000-V Human-Body Model  
(A114-B, Class II)  
Schmitt-Trigger Action Allows Slow Input  
Transition and Better Switching Noise  
Immunity at the Input  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
•
ESD Protection Exceeds ±5000 V With  
Human-Body Model  
(Vhys = 250 mV Typ at 3.3 V)  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
3
4
Q
GND  
CLK  
D
D
CLK  
GND  
V
CC  
1
2
3
5
1
2
3
5
D
CLK  
GND  
V
CC  
2
1
5
V
CC  
4
Q
4
Q
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable  
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range  
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal  
integrity (see Figure 2).  
Switching Characteristics  
Static-Power Consumption  
Dynamic-Power Consumption  
(pF)  
†
at 25 MHz  
(µA)  
3.5  
3
100%  
80%  
100%  
80%  
2.5  
2
Input  
Output  
60%  
40%  
60%  
40%  
3.3-V  
3.3-V  
†  
Logic  
1.5  
1
†
Logic  
0.5  
0
20%  
0%  
20%  
0%  
AUP  
AUP  
−0.5  
20  
Time − ns  
10  
15  
0
5
25  
35 40 45  
30  
†
Single, dual, and triple gates  
†
AUP1G08 data at C = 15 pF  
L
Figure 1. AUP – The Lowest-Power Family  
Figure 2. Excellent Signal Integrity  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
 
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