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SN74AUP1G57DCKTG4 PDF预览

SN74AUP1G57DCKTG4

更新时间： 2024-11-27 05:24:51
品牌 Logo 应用领域
德州仪器 - TI 触发器逻辑集成电路光电二极管栅
页数 文件大小 规格书
18页 548K
描述
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE

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SN74AUP1G57DCKTG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：GREEN, PLASTIC, SC-70, 6 PIN针数：6
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.13Is Samacsys：N
系列：AUP/ULP/VJESD-30 代码：R-PDSO-G6
JESD-609代码：e4长度：2 mm
负载电容（CL）：30 pF逻辑集成电路类型：LOGIC CIRCUIT
最大I（ol）：0.0017 A湿度敏感等级：1
功能数量：1端子数量：6
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP6,.08
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：1.2/3.3 VProp。Delay @ Nom-Sup：26.5 ns
认证状态：Not Qualified施密特触发器：YES
座面最大高度：1.1 mm子类别：Gates
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：0.8 V
标称供电电压 (Vsup)：1.2 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：1.25 mm
Base Number Matches：1

SN74AUP1G57DCKTG4 数据手册

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SN74AUP1G57  
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE  
www.ti.com  
SCES503G–NOVEMBER 2003–REVISED APRIL 2007  
FEATURES  
•
•
•
Available in the Texas Instruments  
NanoFree™ Packages  
•
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
Low Static-Power Consumption  
(ICC = 0.9 µA Max)  
•
•
•
tpd = 5.3 ns Max at 3.3 V  
Suitable for Point-to-Point Applications  
Low Dynamic-Power Consumption  
(Cpd = 4.3 pF Typ at 3.3 V)  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
•
Low Input Capacitance (Ci = 1.5 pF Typ)  
•
ESD Performance Tested Per JESD 22  
Low Noise – Overshoot and Undershoot  
<10% of VCC  
–
2000-V Human-Body Model  
(A114-B, Class II)  
•
Ioff Supports Partial-Power-Down Mode  
Operation  
–
–
200-V Machine Model (A115-A)  
1000-V Charged-Device Model (C101)  
•
•
•
Includes Schmitt-Trigger Inputs  
Wide Operating VCC Range of 0.8 V to 3.6 V  
Optimized for 3.3-V Operation  
•
ESD Protection Exceeds ±5000 V With  
Human-Body Model  
In1  
GND  
In0  
In1  
GND  
In0  
In2  
In2  
In2  
In1  
GND  
In0  
DRY PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(BOTTOM VIEW)  
YFP PACKAGE  
(BOTTOM VIEW)  
In0  
In0  
1
2
3
6
5
4
In1  
GND  
In0  
In2  
VCC  
Y
GND  
In1  
GND  
In1  
In2  
In2  
DESCRIPTION/ORDERING INFORMATION  
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable  
applications. This family ensures a very low static and dynamic power consumption across the entire VCC range  
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity,  
which produces very low undershoot and overshoot characteristics.  
The SN74AUP1G57 features configurable multiple functions. The output state is determined by eight patterns of  
3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter, and noninverter. All  
inputs can be connected to VCC or GND.  
The device functions as an independent gate with Schmitt-trigger inputs, which allow for slow input transition  
and better switching noise immunity at the input.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoFree is a trademark of Texas Instruments.  
UNLESS OTHERWISE NOTED this document contains  
Copyright © 2003–2007, Texas Instruments Incorporated  
PRODUCTION DATA information current as of publication date.  
Products conform to specifications per the terms of Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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SN74AUP1G57DCKTG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUP1G57DCKT TI

完全替代

 LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE
SN74AUP1G57DCKR TI

完全替代

 LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE
SN74AUP1G57DCKRE4 TI

完全替代

 LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE

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