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SN74AUP1G57DRLR

更新时间： 2024-10-01 22:22:43
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
16页 356K
描述
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE

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SN74AUP1G57DRLR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOT
包装说明：VSOF, FL6,.047,20针数：6
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：0.84系列：AUP/ULP/V
JESD-30 代码：R-PDSO-F6JESD-609代码：e4
长度：1.6 mm负载电容（CL）：30 pF
逻辑集成电路类型：LOGIC CIRCUIT最大I（ol）：0.004 A
湿度敏感等级：1功能数量：1
端子数量：6最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：VSOF封装等效代码：FL6,.047,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, VERY THIN PROFILE
包装方法：TR峰值回流温度（摄氏度）：260
电源：1.2/3.3 VProp。Delay @ Nom-Sup：26.5 ns
认证状态：Not Qualified施密特触发器：YES
座面最大高度：0.6 mm子类别：Gates
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：0.8 V
标称供电电压 (Vsup)：1.2 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：FLAT
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：1.2 mm
Base Number Matches：1

SN74AUP1G57DRLR 数据手册

 浏览型号SN74AUP1G57DRLR的Datasheet PDF文件第2页浏览型号SN74AUP1G57DRLR的Datasheet PDF文件第3页浏览型号SN74AUP1G57DRLR的Datasheet PDF文件第4页浏览型号SN74AUP1G57DRLR的Datasheet PDF文件第5页浏览型号SN74AUP1G57DRLR的Datasheet PDF文件第6页浏览型号SN74AUP1G57DRLR的Datasheet PDF文件第7页 
SN74AUP1G57  
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE  
www.ti.com  
SCES503D–NOVEMBER 2003–REVISED JUNE 2005  
FEATURES  
•
•
Optimized for 3.3-V Operation  
•
•
•
Available in the Texas Instruments  
NanoStar™ and NanoFree™ Packages  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
Low Static-Power Consumption (ICC = 0.9 µA  
Max)  
•
•
•
tpd = 5.3 ns Max at 3.3 V  
Suitable for Point-to-Point Applications  
Low Dynamic-Power Consumption  
(Cpd = 4.3 pF Typ at 3.3 V)  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
•
Low Input Capacitance (Ci = 1.5 pF Typ)  
•
ESD Performance Tested Per JESD 22  
Low Noise – Overshoot and Undershoot <10%  
of VCC  
– 2000-V Human-Body Model  
(A114-B, Class II)  
•
Ioff Supports Partial-Power-Down Mode  
Operation  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
•
•
Includes Schmitt-Trigger Inputs  
•
ESD Protection Exceeds ±5000 V With  
Human-Body Model  
Wide Operating VCC Range of 0.8 V to 3.6 V  
YEA, YEP, YZA,  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
OR YZP PACKAGE  
(BOTTOM VIEW)  
3
4
Y
V
In0  
GND  
In1  
1
2
3
6
In1  
GND  
In0  
In2  
V
In1  
GND  
In0  
In2  
V
1
2
3
6
1
2
3
6
In1  
GND  
In0  
In2  
V
2 5  
CC  
5
4
CC  
5
4
CC  
1
6
In2  
Y
CC  
5
4
Y
Y
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable  
applications. This family ensures a very low static and dynamic power consumption across the entire VCC range  
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity,  
which produces very low undershoot and overshoot characteristics.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
NanoStar™ – WCSP (DSBGA)  
0.23-mm Large Bump – YEP  
Tape and reel  
Tape and reel  
SN74AUP1G57YEPR  
_ _ _HH_  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
SN74AUP1G57YZPR  
–40°C to 85°C  
SOT (SOT-23) – DBV  
SOT (SC-70) – DCK  
SOT (SOT-553) – DRL  
Tape and reel  
Tape and reel  
Reel of 4000  
SN74AUP1G57DBVR  
SN74AUP1G57DCKR  
SN74AUP1G57DRLR  
HA7_  
HH_  
HH_  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...16

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SN74AUP1G57DRLR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUP1G57DRLRG4 TI

完全替代

 LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE

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