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SN74AUP1G57DSFR

更新时间： 2024-10-02 06:12:55
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德州仪器 - TI /
页数 文件大小 规格书
24页 1092K
描述
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE

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SN74AUP1G57DSFR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SON
包装说明：VSON, SOLCC6,.04,14针数：6
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.6系列：AUP/ULP/V
JESD-30 代码：S-PDSO-N6JESD-609代码：e4
长度：1 mm负载电容（CL）：30 pF
逻辑集成电路类型：LOGIC CIRCUIT最大I（ol）：0.004 A
湿度敏感等级：1功能数量：1
端子数量：6最高工作温度：85 °C
最低工作温度：-40 °C输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：VSON
封装等效代码：SOLCC6,.04,14封装形状：SQUARE
封装形式：SMALL OUTLINE, VERY THIN PROFILE包装方法：TR
峰值回流温度（摄氏度）：260电源：1.2/3.3 V
Prop。Delay @ Nom-Sup：26.5 ns认证状态：Not Qualified
施密特触发器：YES座面最大高度：0.4 mm
子类别：Gates最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：0.8 V标称供电电压 (Vsup)：1.2 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.35 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：1 mmBase Number Matches：1

SN74AUP1G57DSFR 数据手册

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SN74AUP1G57  
www.ti.com  
SCES503I –NOVEMBER 2003–REVISED MAY 2010  
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE  
Check for Samples: SN74AUP1G57  
1
FEATURES  
•
•
•
Available in the Texas Instruments NanoStar™  
Packages  
•
•
•
Wide Operating VCC Range of 0.8 V to 3.6 V  
Optimized for 3.3-V Operation  
Low Static-Power Consumption  
(ICC = 0.9 mA Max)  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
Low Dynamic-Power Consumption  
(Cpd = 4.3 pF Typ at 3.3 V)  
•
•
•
tpd = 5.3 ns Max at 3.3 V  
Suitable for Point-to-Point Applications  
•
•
Low Input Capacitance (Ci = 1.5 pF Typ)  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Low Noise – Overshoot and Undershoot  
<10% of VCC  
•
ESD Performance Tested Per JESD 22  
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
–
2000-V Human-Body Model  
(A114-B, Class II)  
Includes Schmitt-Trigger Inputs  
–
1000-V Charged-Device Model (C101)  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
ln2  
6
5
4
1
2
3
ln2  
V
ln1  
GND  
ln0  
6
5
4
ln1  
GND  
ln0  
1
2
3
ln1  
GND  
ln0  
1
2
3
ln2  
6
5
4
V
CC  
CC  
Y
V
CC  
Y
Y
DRY PACKAGE  
(TOP VIEW)  
DSF PACKAGE  
(TOP VIEW)  
YFP PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(TOP VIEW)  
A1  
A2  
A1  
A2  
1
2
3
6
5
4
1
6
5
4
1
2
3
6
5
4
1
2
3
6
5
4
In1  
GND  
In0  
In2  
VCC  
Y
In1  
GND  
In0  
In2  
In1  
In1  
GND  
In0  
In2  
VCC  
Y
In2  
B1 2  
B2  
C2  
B1  
C1  
B2  
C2  
VCC  
Y
GND  
In0  
VCC  
Y
C1  
3
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable  
applications. This family ensures a very low static and dynamic power consumption across the entire VCC range  
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity,  
which produces very low undershoot and overshoot characteristics.  
The SN74AUP1G57 features configurable multiple functions. The output state is determined by eight patterns of  
3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter, and noninverter. All  
inputs can be connected to VCC or GND.  
The device functions as an independent gate with Schmitt-trigger inputs, which allow for slow input transition and  
better switching noise immunity at the input.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2010, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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