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SN74ALVCH16901DGGR

更新时间： 2024-11-06 12:49:27
品牌 Logo 应用领域
德州仪器 - TI 总线收发器
页数 文件大小 规格书
14页 368K
描述
18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS

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中文翻译

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SN74ALVCH16901DGGR 数据手册

 浏览型号SN74ALVCH16901DGGR的Datasheet PDF文件第2页浏览型号SN74ALVCH16901DGGR的Datasheet PDF文件第3页浏览型号SN74ALVCH16901DGGR的Datasheet PDF文件第4页浏览型号SN74ALVCH16901DGGR的Datasheet PDF文件第5页浏览型号SN74ALVCH16901DGGR的Datasheet PDF文件第6页浏览型号SN74ALVCH16901DGGR的Datasheet PDF文件第7页 
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SCES010F − JULY 1995 − REVISED SEPTEMBER 2004  
DGG PACKAGE  
(TOP VIEW)  
D
D
Member of the Texas Instruments  
WidebusFamily  
UBT Transceiver Combines D-Type  
Latches and D-Type Flip-Flops for  
Operation in Transparent, Latched, or  
Clocked Mode  
1
64  
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1CLKENAB  
LEAB  
CLKAB  
1ERRA  
1APAR  
GND  
1CLKENBA  
LEBA  
CLKBA  
1ERRB  
1BPAR  
GND  
2
3
4
D
D
D
D
Operates From 1.65 V to 3.6 V  
5
Max t of 4.4 ns at 3.3 V  
pd  
24-mA Output Drive at 3.3 V  
6
7
1A1  
1A2  
1A3  
1B1  
8
1B2  
Simultaneously Generates and Checks  
Parity  
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1B3  
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32  
V
V
CC  
CC  
D
Option to Select Generate Parity and Check  
or Feed-Through Data/Parity in A-to-B or  
B-to-A Directions  
1A4  
1A5  
1A6  
GND  
1A7  
1A8  
2A1  
2A2  
GND  
2A3  
2A4  
2A5  
1B4  
1B5  
1B6  
GND  
1B7  
1B8  
2B1  
2B2  
GND  
2B3  
2B4  
2B5  
D
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
D
D
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
description/ordering information  
V
V
CC  
CC  
2A6  
2A7  
2A8  
GND  
2APAR  
2ERRA  
OEAB  
SEL  
2B6  
2B7  
2B8  
GND  
2BPAR  
2ERRB  
OEBA  
ODD/EVEN  
2CLKENBA  
This 18-bit (dual-octal) noninverting registered  
transceiver is designed for 1.65-V to 3.6-V V  
operation.  
CC  
The SN74ALVCH16901 is a dual 9-bit to dual 9-bit  
parity transceiver with registers. The device can  
operate as a feed-through transceiver or it can  
generate/check parity from the two 8-bit data  
buses in either direction.  
2CLKENAB  
The SN74ALVCH16901 features independent  
clock (CLKAB or CLKBA), latch-enable (LEAB or  
LEBA), and dual 9-bit clock-enable (CLKENAB or CLKENBA) inputs. It also provides parity-enable (SEL) and  
parity-select (ODD/EVEN) inputs and separate error-signal (ERRA or ERRB) outputs for checking parity. The  
direction of data flow is controlled by OEAB and OEBA. When SEL is low, the parity functions are enabled. When  
SEL is high, the parity functions are disabled, and the device acts as an 18-bit registered transceiver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
A
PACKAGE  
−40°C to 85°C TSSOP − DGG  
Tape and reel  
SN74ALVCH16901DGGR  
ALVCH16901  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and UBT are trademarks of Texas Instruments.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...14

中文翻译

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SN74ALVCH16901DGGR 替代型号

型号 品牌 替代类型 描述 数据表
74ALVCH16901DGGRG4 TI

完全替代

 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS

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