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SN74ALVCH16903DGG

更新时间： 2024-11-19 23:09:43
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德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
12页 185K
描述
3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS

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SN74ALVCH16903DGG 数据手册

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SN74ALVCH16903  
3.3-V 12-BIT UNIVERSAL BUS DRIVER  
WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS  
SCES095C – MARCH 1997 – REVISED MAY 1998  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
OE  
1Y1  
1Y2  
GND  
2Y1  
2Y2  
CLK  
1
56  
2
55 1A  
Checks Parity  
3
54 11A/YERREN  
Able to Cascade With a Second  
SN74ALVCH16903  
GND  
4
53  
5
52 11Y1  
51 11Y2  
6
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
V
7
50  
V
CC  
CC  
3Y1  
3Y2  
4Y1  
GND  
4Y2  
5Y1  
5Y2  
6Y1  
6Y2  
7Y1  
GND  
7Y2  
8Y1  
8Y2  
8
49 2A  
48 3A  
9
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
4A  
GND  
12A  
12Y1  
12Y2  
5A  
6A  
7A  
GND  
APAR  
8A  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), and Thin Very  
Small-Outline (DGV) Packages  
description  
YERR  
This 12-bit universal bus driver is designed for  
2.3-V to 3.6-V V operation.  
V
V
CC  
CC  
CC  
9Y1  
9Y2  
GND  
10Y1  
10Y2  
9A  
MODE  
GND  
10A  
PARI/O  
CLKEN  
The SN74ALVCH16903 has dual outputs and can  
operate as a buffer or an edge-triggered register.  
In both modes, parity is checked on APAR, which  
arrives one cycle after the data to which it applies.  
The YERR output, which is produced one cycle  
after APAR, is open drain.  
PAROE  
MODEselects one of the two data paths. When MODE is low, the device operates as an edge-triggered register.  
On the positive transition of the clock (CLK) input and when the clock-enable (CLKEN) input is low, data set up  
at the A inputs is stored in the internal registers. On the positive transition of CLK and when CLKEN is high, only  
data set up at the 9A–12A inputs is stored in their internal registers. When MODE is high, the device operates  
as a buffer and data at the A inputs passes directly to the outputs. 11A/YERREN serves a dual purpose; it acts  
as a normal data bit and also enables YERR data to be clocked into the YERR output register.  
When used as a single device, parity output enable (PAROE) must be tied high; when parity input/output  
(PARI/O) is low, even parity is selected and when PARI/O is high, odd parity is selected. When used in pairs  
and PAROE is low, the parity sum is output on PARI/O for cascading to the second SN74ALVCH16903. When  
used in pairs and PAROE is high, PARI/O accepts a partial parity sum from the first SN74ALVCH16903.  
A buffered output-enable (OE) input can be used to place the 24 outputs and YERR in either a normal logic state  
(high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor  
drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive  
bus lines without need for interface or pullup components.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

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