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SN74ALVCH16952

更新时间： 2024-11-17 23:09:43
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德州仪器 - TI 输出元件
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11页 165K
描述
16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS

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SN74ALVCH16952 数据手册

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SN74ALVCH16952  
16-BIT REGISTERED TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCES011D – JULY 1995 – REVISED FEBRUARY 1999  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1OEAB  
1CLKAB  
1CLKENAB  
GND  
1OEBA  
1
56  
2
55 1CLKBA  
54 1CLKENBA  
53 GND  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
3
4
1A1  
5
52 1B1  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
1A2  
6
51 1B2  
V
7
50  
V
CC  
CC  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
8
49 1B3  
48 1B4  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1B5  
GND  
1B6  
1B7  
1B8  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), and Thin Very  
Small-Outline (DGV) Packages  
description  
This 16-bit registered transceiver is designed for  
1.65-V to 3.6-V V operation.  
CC  
The SN74ALVCH16952 contains two sets of  
D-type flip-flops for temporary storage of data  
flowing in either direction. This device can be used  
as two 8-bit transceivers or one 16-bit transceiver.  
Data on the A or B bus is stored in the registers on  
the low-to-high transition of the clock (CLKAB or  
CLKBA) input provided that the clock-enable  
(CLKENAB or CLKENBA) input is low. Taking the  
output-enable (OEAB or OEBA) input low  
accesses the data on either port.  
V
V
CC  
CC  
2A7  
2A8  
GND  
2B7  
2B8  
GND  
2CLKENBA  
2CLKBA  
2OEBA  
2CLKENAB  
2CLKAB  
2OEAB  
To ensure the high-impedance state during power  
up or power down, OE should be tied to V  
CC  
through a pullup resistor; the minimum value of  
the resistor is determined by the current-sinking  
capability of the driver.  
Active bus-hold circuitry is provided to hold  
unused or floating data inputs at a valid logic level.  
The SN74ALVCH16952 is characterized for  
operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and EPIC are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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SN74ALVCH16952DGV TI

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 		16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SN74ALVCH16952DGVR ROCHESTER

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 		ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC,
SN74ALVCH16952DGVR TI

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 		16-Bit Registered Transceiver With 3-State Outputs 56-TVSOP -40 to 85
SN74ALVCH16952DL TI

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 		16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SN74ALVCH16952DL ROCHESTER

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 		ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, GRE
SN74ALVCH16952DLR ROCHESTER

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 		ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, GRE

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