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SN74ALVCH16973DGVR PDF预览

SN74ALVCH16973DGVR

更新时间： 2024-09-16 05:29:35
品牌 Logo 应用领域
德州仪器 - TI 总线收发器锁存器
页数 文件大小 规格书
13页 186K
描述
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH FOUR INDEPENDENT BUFFERS

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SN74ALVCH16973DGVR 数据手册

 浏览型号SN74ALVCH16973DGVR的Datasheet PDF文件第2页浏览型号SN74ALVCH16973DGVR的Datasheet PDF文件第3页浏览型号SN74ALVCH16973DGVR的Datasheet PDF文件第4页浏览型号SN74ALVCH16973DGVR的Datasheet PDF文件第5页浏览型号SN74ALVCH16973DGVR的Datasheet PDF文件第6页浏览型号SN74ALVCH16973DGVR的Datasheet PDF文件第7页 
SN74ALVCH16973  
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH  
WITH FOUR INDEPENDENT BUFFERS  
www.ti.com  
SCES435B–APRIL 2003–REVISED SEPTEMBER 2004  
FEATURES  
DGG, DGV, OR DL PACKAGE  
•
•
•
•
Member of the Texas Instruments Widebus™  
Family  
(TOP VIEW)  
1
48 DIR  
47 B1  
46  
TOE  
D1  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
2
3
Q1  
A1  
GND  
Y1  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
4
45 GND  
44 B2  
5
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
6
43 Q2  
A2  
7
42  
41  
40  
39  
V
CC  
V
CC  
8
B3  
Q3  
GND  
D2  
A3  
GND  
Y2  
A4  
D3  
– 1000-V Charged-Device Model (C101)  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
DESCRIPTION/ORDERING INFORMATION  
38 B4  
37 Q4  
36 B5  
This device contains four independent noninverting  
buffers and an 8-bit noninverting bus transceiver and  
D-type latch, designed for 1.65-V to 3.6-V VCC  
operation.  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
Q5  
GND  
B6  
A5  
GND  
Y3  
The SN74ALVCH16973 is particularly suitable for  
demultiplexing an address/data bus into a dedicated  
address bus and dedicated data bus. The device is  
used where there is asynchronous bidirectional  
communication between the A and B data bus, and  
the address signals are latched and buffered on the  
Q bus. The control-function implementation minimizes  
external timing requirements.  
Q6  
A6  
V
CC  
V
CC  
B7  
Q7  
GND  
Q8  
B8  
D4  
A7  
GND  
A8  
Y4  
LE  
LOE  
This device can be used as one 4-bit buffer, one 8-bit  
transceiver, or one 8-bit latch. It allows data  
transmission from the A bus to the B bus or from the  
B bus to the A bus, depending on the logic level at  
the direction-control (DIR) input. The transceiver  
output-enable (TOE) input can be used to disable the  
transceivers so that the A and B buses effectively are  
isolated.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74ALVCH16973DL  
TOP-SIDE MARKING  
Tube  
SSOP - DL  
ALVCH16973  
Tape and reel  
SN74ALVCH16973DLR  
SN74ALVCH16973DGGR  
SN74ALVCH16973DGVR  
-40°C to 85°C  
TSSOP - DGG  
TVSOP - DGV  
Tape and reel  
Tape and reel  
ALVCH16973  
VH973  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...13

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SN74ALVCH16973DGVR 替代型号

型号 品牌 替代类型 描述 数据表
74ALVCH16973DGVRE4 TI

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 8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH FOUR INDEPENDENT BUFFERS

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