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SN65LVDS1224DB PDF预览

SN65LVDS1224DB

更新时间： 2024-09-13 20:07:15
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德州仪器 - TI /
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SN65LVDS1224DB

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中文翻译

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SN65LVDS1224DB 技术参数

生命周期：Obsolete包装说明：,
Reach Compliance Code：unknown风险等级：5.84
Base Number Matches：1

SN65LVDS1224DB 数据手册

 浏览型号SN65LVDS1224DB的Datasheet PDF文件第2页浏览型号SN65LVDS1224DB的Datasheet PDF文件第3页浏览型号SN65LVDS1224DB的Datasheet PDF文件第4页浏览型号SN65LVDS1224DB的Datasheet PDF文件第5页浏览型号SN65LVDS1224DB的Datasheet PDF文件第6页浏览型号SN65LVDS1224DB的Datasheet PDF文件第7页 
SN65LVDS1023/SN65LVDS1224  
30 MHz TO 66 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER  
SLLS527 – FEBRUARY 2002  
300–660 Mbps Serial LVDS Data Payload  
Lock Indicator  
Bandwidth at 30 MHz to 66 MHz System  
Clock  
No External Components Required for PLL  
Low-Cost 28-Pin SSOP Package  
Industrial Temperature Qualified,  
Pin-Compatible Superset of NSM  
DS92LV1023/DS92LV1224  
T = –40°C to 85°C  
A
Chipset (Serializer/Deserializer) Power  
Consumption <400 mW (Typ) at 66 MHz  
Programmable Edge Trigger on Clock  
Flow-Through Pinout for Easy PCB Layout  
Synchronization Mode for Faster Lock  
SN65LVDS1023  
Serializer  
SN65LVDS1224  
Deserializer  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
SYNC1  
SYNC2  
DV  
DV  
AV  
AGND  
PWRDN  
AGND  
AGND  
RCLK_R/F  
REFCLK  
R
R
R
R
R
0
1
2
3
4
CC  
CC  
CC  
OUT  
OUT  
OUT  
OUT  
OUT  
2
2
3
3
D
D
D
D
D
D
D
D
D
D
0
1
2
3
4
5
6
7
8
9
IN  
IN  
IN  
IN  
IN  
IN  
IN  
IN  
IN  
IN  
4
4
AV  
CC  
5
5
R +  
I
6
6
R –  
DV  
DGND  
DV  
I
CC  
7
7
D +  
PWRDN  
REN  
RCLK  
LOCK  
O
8
8
D –  
O
CC  
9
9
AGND  
DEN  
AGND  
DGND  
10  
11  
12  
13  
14  
10  
11  
12  
13  
14  
R
R
R
R
R
5
6
7
8
9
OUT  
OUT  
OUT  
OUT  
OUT  
AV  
CC  
AV  
AGND  
AGND  
DGND  
CC  
TCLK_R/F  
TCLK  
DGND  
DGND  
description  
The SN65LVDS1023 serializer and SN65LVDS1224 deserializer comprise a 10-bit serdes chipset designed to  
transmit and receive serial data over LVDS differential backplanes, at equivalent parallel word rates from  
30 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 360 Mbps and 792 Mbps  
payload encoded throughput.  
Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC  
patterns, or the deserializer can be allowed to synchronize to random data. By using the synchronization mode,  
the deserializer establishes lock within specified, shorter time parameters.  
The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is  
available to place the output pins in the high-impedance state without losing PLL lock.  
The SN65LVDS1023 and SN65LVDS1224 are characterized for operation over ambient air temperature of  
–40°C to 85°C.  
ORDERING INFORMATION  
DEVICE  
Serializer  
PART NUMBER  
SN65LVDS1023DB  
SN65LVDS1224DB  
Deserializer  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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