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SN65LVDS151DA PDF预览

SN65LVDS151DA

更新时间: 2024-01-24 05:09:35
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德州仪器 - TI /
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描述
MuxIt SERIALIZER-TRANSMITTER

SN65LVDS151DA 数据手册

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SN65LVDS151  
MuxIt SERIALIZER-TRANSMITTER  
SLLS444A – DECEMBER 2000  
SN65LVDS151DA  
D
A Member of the MuxIt  
Serializer-Deserializer Building-Block Chip  
Family  
(Marked as 65LVDS151)  
CI–  
V
1
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
CC  
D
D
D
Supports Serialization of up to 10 Bits of  
Parallel Data Input at Rates up to 200 Mbps  
CI+  
GND  
LCRI+  
LCRI–  
CI_EN  
DI–9  
2
LVI  
3
PLL Lock/Valid Input Provided to Enable  
Link Data Transfers  
MCI–  
MCI+  
GND  
4
5
Cascadable With Additional SN65LVDS151  
MuxIt Serializer-Transmitters for Wider  
Parallel Input Data Channel Widths  
6
V
DI–8  
7
CC  
LCO+  
LCO–  
DI–7  
8
DI–6  
D
LVDS Compatible Differential Inputs and  
Outputs Meet or Exceed the Requirements  
of ANSI TIA/EIA-644-A  
9
V
DI–5  
10  
11  
12  
CC  
EN  
DI–4  
LCO_EN  
VCC5  
GND  
DO+  
DI–3  
D
D
LVDS Inputs and Outputs ESD Protection  
Exceeds 12 kV HBM  
DI–2 13  
DI–1 14  
DI–0 15  
LVTTL Compatible Inputs for Lock/Valid,  
Enables, and Parallel Data Inputs Are 5-V  
Tolerant  
DO–  
16  
GND  
D
D
Operates With 3.3 V Supply  
Packaged in 32-Pin DA Thin Shrink  
Small-Outline Package With 26 Mil Terminal  
Pitch  
description  
MuxIt is a family of general-purpose, multiple-chip building blocks for implementing parallel data serializers and  
deserializers. The system allows for wide parallel data to be transmitted through a reduced number of  
transmission lines over distances greater than can be achieved with a single-ended (e.g., LVTTL or LVCMOS)  
data interface. The number of bits multiplexed per transmission line is user-selectable and allows for higher  
transmission efficiencies than with existing fixed ratio solutions. MuxIt utilizes the LVDS (TIA/EIA-644-A) low  
voltage differential signaling technology for communications between the data source and data destination.  
The MuxIt family initially includes three devices supporting simplex communications: the SN65LVDS150 phase  
locked loop frequency multiplier, the SN65LVDS151 serializer-transmitter, and the SN65LVDS152  
receiver-deserializer.  
The SN65LVDS151 consists of a 10-bit parallel-in/serial-out shift register, three LVDS differential transmission  
line receivers, a pair of LVDS differential transmission line drivers, plus associated input buffers. It accepts up  
to10bitsofuserdataonparalleldatainputs(DI–0DI–9)andserializes(multiplexes)thedatafortransmission  
over an LVDS transmission line link. Two or more SN65LVDS151 units may be connected in series (cascaded)  
to accommodate wider parallel data paths for higher serialization values. Data is transmitted over the LVDS  
serial link at M times the input parallel data clock frequency. The multiplexing ratio M, or number of bits per data  
clock cycle, is programmed on the companion SN65LVDS150 MuxIt programmable PLL frequency multiplier  
with configuration pins (M1 M5). The range of multiplexing ratio M supported by the SN65LVDS150 MuxIt  
programmable PLL frequency multiplier is between 4 and 40. Table 1 shows some of the combinations of LCRI  
and MCI supported by the SN65LVDS150 MuxIt programmable PLL frequency multiplier.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
MuxIt is a trademark of Texas Instruments.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN65LVDS151DA 替代型号

型号 品牌 替代类型 描述 数据表
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