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SN65LVDS16DRFTG4 PDF预览

SN65LVDS16DRFTG4

更新时间： 2024-11-23 23:03:07
品牌 Logo 应用领域
德州仪器 - TI 振荡器转换器电平转换器驱动程序和接口锁存器接口集成电路光电二极管信息通信管理
页数 文件大小 规格书
15页 314K
描述
2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS

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SN65LVDS16DRFTG4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：SON
包装说明：2 X 2 MM, GREEN, PLASTIC, SON-8针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.58
Is Samacsys：N其他特性：IT ALSO OPERATES AT 3.3 V SUPPLY
最大延迟：0.63 ns接口集成电路类型：PECL TO LVDS TRANSLATOR
JESD-30 代码：S-PDSO-N8JESD-609代码：e4
长度：2 mm湿度敏感等级：1
位数：1功能数量：1
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C输出锁存器或寄存器：NONE
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：HVSSON封装等效代码：SOLCC8,.08,20
封装形状：SQUARE封装形式：SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：2.5/3.3 V
认证状态：Not Qualified座面最大高度：0.8 mm
子类别：Other Interface ICs最大供电电压：3.6 V
最小供电电压：2.375 V标称供电电压：2.5 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：2 mmBase Number Matches：1

SN65LVDS16DRFTG4 数据手册

 浏览型号SN65LVDS16DRFTG4的Datasheet PDF文件第2页浏览型号SN65LVDS16DRFTG4的Datasheet PDF文件第3页浏览型号SN65LVDS16DRFTG4的Datasheet PDF文件第4页浏览型号SN65LVDS16DRFTG4的Datasheet PDF文件第5页浏览型号SN65LVDS16DRFTG4的Datasheet PDF文件第6页浏览型号SN65LVDS16DRFTG4的Datasheet PDF文件第7页 
SN65LVDS16, SN65LVP16  
SN65LVDS17, SN65LVP17  
www.ti.com  
SLLS625B–SEPTEMBER 2004–REVISED NOVEMBER 2005  
2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS  
FEATURES  
•
2-mm × 2-mm Small-Outline  
No-Lead Package  
•
Low-Voltage PECL Input and Low-Voltage  
PECL or LVDS Outputs  
APPLICATIONS  
•
•
•
Clock Rates to 2 GHz  
PECL-to-LVDS Translation  
Clock Signal Amplification  
– 140-ps Output Transition Times  
– 0.11 ps Typical Intrinsic Phase Jitter  
– Less than 630 ps Propagation Delay Times  
2.5-V or 3.3-V Supply Operation  
•
DESCRIPTION  
These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain  
outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on  
the SN65LVx16) and fully differential inputs on the SN65LVx17.  
The SN65LVx16 provides the user a Gain Control (GC) for controlling the Q output from 300 mV to 860 mV  
either by leaving it open (NC), grounded, or tied to VCC. (When left open, the Q output defaults to 575 mV.) The  
Q on the SN65LVx17 defaults to 575 mV as well.  
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCC for use in receiving single-ended  
PECL input signals. When not used, VBB should be unconnected or open.  
All devices are characterized for operation from –40°C to 85°C.  
SN65LVDS17, SN65LVP17  
4 mA  
SN65LVDS16, SN65LVP16  
4 mA  
Q
Q
A
Y
Z
A
B
Y
Z
V
BB  
V
V
REF  
V
CC  
V
BB  
V
CC  
REF  
EN  
EN  
GC  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2004–2005, Texas Instruments Incorporated  
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SN65LVDS16DRFTG4 替代型号

型号 品牌 替代类型 描述 数据表
SN65LVDS16DRFT TI

类似代替

 2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS

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