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SN65LVDS152DARG4 PDF预览

SN65LVDS152DARG4

更新时间： 2024-01-05 20:40:43
品牌 Logo 应用领域
德州仪器 - TI 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
17页 243K
描述
MuxIt RECEIVER-DESERIALIZER

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中文翻译

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SN65LVDS152DARG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：0.65 MM PITCH, GREEN, TSSOP-32针数：32
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.5
Is Samacsys：N驱动器位数：1
输入特性：DIFFERENTIAL接口集成电路类型：LINE RECEIVER
接口标准：EIA-644-A; TIA-644-AJESD-30 代码：R-PDSO-G32
JESD-609代码：e4长度：11 mm
湿度敏感等级：2功能数量：1
端子数量：32最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP32,.3
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified最大接收延迟：5.5 ns
接收器位数：1座面最大高度：1.2 mm
子类别：Line Driver or Receivers最大压摆率：60 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6.2 mm
Base Number Matches：1

SN65LVDS152DARG4 数据手册

 浏览型号SN65LVDS152DARG4的Datasheet PDF文件第2页浏览型号SN65LVDS152DARG4的Datasheet PDF文件第3页浏览型号SN65LVDS152DARG4的Datasheet PDF文件第4页浏览型号SN65LVDS152DARG4的Datasheet PDF文件第5页浏览型号SN65LVDS152DARG4的Datasheet PDF文件第6页浏览型号SN65LVDS152DARG4的Datasheet PDF文件第7页 
SN65LVDS152  
MuxIt RECEIVER-DESERIALIZER  
SLLS445 – DECEMBER 2000  
SN65LVDS152DA  
(Marked as 65LVDS152)  
D
D
A Member of the MuxItt Serializer-  
Deserializer Building-Block Chip Family  
(TOP VIEW)  
Supports Deserialization of One Serial Link  
Data Channel Input at Rates up to  
200 Mbps  
DI+  
DI–  
V
CC  
LVI  
1
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
2
D
D
PLL Lock/Valid Input Provided to Enable  
Parallel Data and Clock Outputs  
GND  
3
MCI–  
MCI+  
GND  
LCI+  
4
5
LCI–  
Cascadable With Additional SN65LVDS152  
MuxIt Receiver–Deserializers for Wider  
Parallel Output Data Channel Widths  
6
GND  
DCO  
7
CO_EN  
DO–9  
DO–8  
DO–7  
DO–6  
DO–5  
DO–4  
DO–3  
DO–2  
DO–1  
DO–0  
8
V
CC  
D
LVDS Compatible Differential Inputs and  
Outputs Meet or Exceed the Requirements  
of ANSI TIA/EIA-644-A  
9
GND  
10  
11  
12  
13  
14  
15  
16  
V
CC  
V
CC  
D
D
LVDS Input and Output ESD Protection  
Exceeds 12 kV HBM  
GND  
GND  
EN  
LVTTL Compatible Inputs for Lock/Valid  
and Enables Are 5-V Tolerant  
CO–  
CO+  
D
Operates With 3.3-V Supply  
D
Packaged in 32-Pin DA Thin Shrink Small-  
Outline Package With 26-Mil Terminal Pitch  
description  
MuxIt is a family of general-purpose, multiple-chip building blocks for implementing parallel data serializers and  
deserializers. The system allows for wide parallel data to be transmitted through a reduced number of  
transmission lines over distances greater than can be achieved with a single-ended (e.g., LVTTL or LVCMOS)  
data interface. The number of bits multiplexed per transmission line is user selectable, allowing for higher  
transmission efficiencies than with other existing fixed ratio solutions. MuxIt utilizes the LVDS (TIA/EIA-644-A)  
low voltage differential signaling technology for communications between the data source and data destination.  
The MuxIt family initially includes three devices supporting simplex communications: the SN65LVDS150 phase  
locked loop frequency multiplier, the SN65LVDS151 serializer-transmitter, and the SN65LVDS152 receiver-  
deserializer.  
The SN65LVDS152 consists of three LVDS differential transmission line receivers, an LVDS differential  
transmission line driver, a 10-bit serial-in/parallel-out shift register, plus associated input and output buffers. It  
receives serialized data over an LVDS transmission line link, deserializes (demultiplexes) it, and delivers it on  
parallel data outputs, DO–0 through DO–9. Data received over the link is clocked at a factor of M times the  
original parallel data frequency. The multiplexing ratio M, or number of bits per data clock cycle, is programmed  
with configuration pins (M1 → M5) on the companion SN65LVDS150 MuxIt programmable PLL frequency  
multiplier. Up to 10 bits of data may be deserialized and output by each SN65LVDS152. Two or more  
SN65LVDS152 units may be connected in series (cascaded) to accommodate wider parallel data paths for  
higher serialization values. The range of multiplexing ratio M supported by the SN65LVDS150 MuxIt  
programmable PLL frequency multiplier is between 4 and 40. Table 1 shows some of the combinations of LCI  
and MCI supported by the SN65LVDS150 MuxIt programmable PLL frequency multiplier.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
MuxIt is a trademark of Texas Instruments.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...17

中文翻译

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SN65LVDS152DARG4 替代型号

型号 品牌 替代类型 描述 数据表
SN65LVDS152DAG4 TI

功能相似

 LINE RECEIVER, PDSO32, 0.65 MM PITCH, GREEN, TSSOP-32
SN65LVDS152DAR TI

功能相似

 MuxIt RECEIVER-DESERIALIZER
SN65LVDS152DA TI

功能相似

 MuxIt RECEIVER-DESERIALIZER

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