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SN54LVTH2952 PDF预览

SN54LVTH2952

更新时间： 2024-11-19 23:03:07
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德州仪器 - TI 总线收发器输出元件
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8页 126K
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3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

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SN54LVTH2952 数据手册

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SN54LVTH2952, SN74LVTH2952  
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS  
WITH 3-STATE OUTPUTS  
SCBS710D – OCTOBER 1997 – REVISED APRIL 1999  
SN54LVTH2952 . . . JT PACKAGE  
SN74LVTH2952 . . . DB, DGV, DW, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
B8  
B7  
V
CC  
A8  
1
24  
23  
I
and Power-Up 3-State Support Hot  
2
off  
Insertion  
B6  
B5  
B4  
3
22 A7  
21 A6  
20 A5  
4
Bus-Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
5
6
19  
18  
17  
16  
15  
14  
13  
B3  
B2  
B1  
A4  
A3  
A2  
A1  
OEBA  
CLKBA  
CLKENBA  
7
Support Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
8
9
OEAB  
CLKAB  
CLKENAB  
GND  
3.3-V V  
)
CC  
10  
11  
12  
Support Unregulated Battery Operation  
Down to 2.7 V  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
SN54LVTH2952 . . . FK PACKAGE  
(TOP VIEW)  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
4
3
2
1
28 27 26  
25  
5
6
7
8
9
B5  
B4  
B3  
NC  
B2  
A6  
A5  
A4  
NC  
A3  
A2  
A1  
24  
23  
22  
21  
20  
19  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW), and  
Thin Very Small-Outline (DGV) Packages,  
Ceramic Chip Carriers (FK), and Ceramic  
(JT) DIPs  
10  
11  
B1  
OEAB  
12 13 14 15 16 17 18  
description  
These octal bus transceivers and registers are  
designed specifically for low-voltage (3.3-V) V  
CC  
operation, but with the capability to provide a TTL  
interface to a 5-V system environment.  
NC – No internal connection  
The ’LVTH2952 devices consist of two 8-bit back-to-back registers that store data flowing in both directions  
between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition  
of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB or CLKENBA) input is low.  
Taking the output-enable (OEAB or OEBA) input low accesses the data on either port.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
When V is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V  
through a pullup resistor;  
CC  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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