Datasheet > SN54LVTH2952

SN54LVTH2952

更新时间： 2024-09-15 23:03:07

品牌	Logo	应用领域
德州仪器 - TI		总线收发器输出元件
页数	文件大小	规格书
8页	126K
描述
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

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SN54LVTH2952 数据手册

SN54LVTH2952, SN74LVTH2952

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS710D – OCTOBER 1997 – REVISED APRIL 1999

SN54LVTH2952 . . . JT PACKAGE

SN74LVTH2952 . . . DB, DGV, DW, OR PW PACKAGE

(TOP VIEW)

State-of-the-Art Advanced BiCMOS

Technology (ABT) Design for 3.3-V

Operation and Low Static-Power

Dissipation

and Power-Up 3-State Support Hot

off

Insertion

22 A7

21 A6

20 A5

Bus-Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

OEBA

CLKBA

CLKENBA

Support Mixed-Mode Signal Operation

(5-V Input and Output Voltages With

OEAB

CLKAB

CLKENAB

GND

3.3-V V

)

Support Unregulated Battery Operation

Down to 2.7 V

Typical V

< 0.8 V at V

(Output Ground Bounce)

OLP

= 3.3 V, T = 25°C

SN54LVTH2952 . . . FK PACKAGE

(TOP VIEW)

Latch-Up Performance Exceeds 500 mA Per

JESD 17

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

28 27 26

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), Thin Shrink Small-Outline (PW), and

Thin Very Small-Outline (DGV) Packages,

Ceramic Chip Carriers (FK), and Ceramic

(JT) DIPs

OEAB

12 13 14 15 16 17 18

description

These octal bus transceivers and registers are

designed specifically for low-voltage (3.3-V) V

operation, but with the capability to provide a TTL

interface to a 5-V system environment.

NC – No internal connection

The ’LVTH2952 devices consist of two 8-bit back-to-back registers that store data flowing in both directions

between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition

of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB or CLKENBA) input is low.

Taking the output-enable (OEAB or OEBA) input low accesses the data on either port.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

When V is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 1.5 V, OE should be tied to V

through a pullup resistor;

the minimum value of the resistor is determined by the current-sinking capability of the driver.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7 8

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与SN54LVTH2952相关器件

型号	品牌	获取价格	描述	数据表
SN54LVTH2952_15	TI	获取价格	3.3-V ABT OCTAL BUS RANSCEIVERS AND REGISTERS
SN54LVTH2952FK	TI	获取价格	3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54LVTH2952JT	TI	获取价格	3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54LVTH373	TI	获取价格	3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVTH373_07	TI	获取价格	3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVTH373_08	TI	获取价格	3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVTH373FK	TI	获取价格	3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVTH373J	TI	获取价格	3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVTH373W	TI	获取价格	3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVTH374	TI	获取价格	3.3 V ABT OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS

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