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SN54LVTH373J

更新时间： 2024-11-19 23:03:07
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路输出元件信息通信管理
页数 文件大小 规格书
7页 112K
描述
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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SN54LVTH373J 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：20
Reach Compliance Code：unknown风险等级：5.39
系列：LVTJESD-30 代码：R-GDIP-T20
长度：24.195 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE最大电源电流（ICC）：5 mA
传播延迟（tpd）：5.1 ns认证状态：Not Qualified
座面最大高度：5.08 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：NO技术：BICMOS
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

SN54LVTH373J 数据手册

 浏览型号SN54LVTH373J的Datasheet PDF文件第2页浏览型号SN54LVTH373J的Datasheet PDF文件第3页浏览型号SN54LVTH373J的Datasheet PDF文件第4页浏览型号SN54LVTH373J的Datasheet PDF文件第5页浏览型号SN54LVTH373J的Datasheet PDF文件第6页浏览型号SN54LVTH373J的Datasheet PDF文件第7页 
SN54LVTH373, SN74LVTH373  
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCBS689E – MAY 1997 – REVISED APRIL 1999  
SN54LVTH373 . . . J OR W PACKAGE  
SN74LVTH373 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
OE  
1Q  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
I
and Power-Up 3-State Support Hot  
off  
8Q  
8D  
7D  
Insertion  
1D  
2D  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
2Q  
3Q  
16 7Q  
15 6Q  
14  
13  
12  
11  
3D  
4D  
4Q  
GND  
6D  
5D  
5Q  
LE  
Support Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
3.3-V V  
)
CC  
Support Unregulated Battery Operation  
Down to 2.7 V  
SN54LVTH373 . . . FK PACKAGE  
(TOP VIEW)  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
3
2
1 20 19  
18  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
6Q  
4
5
6
7
8
17  
16  
15  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Ceramic Flat (W) Package, and Ceramic (J)  
DIPs  
14 6D  
9 10 11 12 13  
description  
These octal latches are designed specifically for low-voltage (3.3-V) V  
provide a TTL interface to a 5-V system environment.  
operation, but with the capability to  
CC  
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the  
Q outputs are latched at the logic levels set up at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without need for interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
When V is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V  
through a pullup resistor;  
CC  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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