5秒后页面跳转
捷配首页

Datasheet > SN54LVTH2952JT
SN54LVTH2952JT PDF预览

SN54LVTH2952JT

更新时间： 2024-11-19 23:03:07
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
8页 126K
描述
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

SN54LVTH2952JT 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：24
Reach Compliance Code：unknown风险等级：5.84
其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION系列：LVT
JESD-30 代码：R-GDIP-T24长度：32.005 mm
负载电容（CL）：50 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
最大电源电流（ICC）：5 mA传播延迟（tpd）：5.5 ns
认证状态：Not Qualified座面最大高度：5.08 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：NO
技术：BICMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

SN54LVTH2952JT 数据手册

 浏览型号SN54LVTH2952JT的Datasheet PDF文件第2页浏览型号SN54LVTH2952JT的Datasheet PDF文件第3页浏览型号SN54LVTH2952JT的Datasheet PDF文件第4页浏览型号SN54LVTH2952JT的Datasheet PDF文件第5页浏览型号SN54LVTH2952JT的Datasheet PDF文件第6页浏览型号SN54LVTH2952JT的Datasheet PDF文件第7页 
SN54LVTH2952, SN74LVTH2952  
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS  
WITH 3-STATE OUTPUTS  
SCBS710D – OCTOBER 1997 – REVISED APRIL 1999  
SN54LVTH2952 . . . JT PACKAGE  
SN74LVTH2952 . . . DB, DGV, DW, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
B8  
B7  
V
CC  
A8  
1
24  
23  
I
and Power-Up 3-State Support Hot  
2
off  
Insertion  
B6  
B5  
B4  
3
22 A7  
21 A6  
20 A5  
4
Bus-Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
5
6
19  
18  
17  
16  
15  
14  
13  
B3  
B2  
B1  
A4  
A3  
A2  
A1  
OEBA  
CLKBA  
CLKENBA  
7
Support Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
8
9
OEAB  
CLKAB  
CLKENAB  
GND  
3.3-V V  
)
CC  
10  
11  
12  
Support Unregulated Battery Operation  
Down to 2.7 V  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
SN54LVTH2952 . . . FK PACKAGE  
(TOP VIEW)  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
4
3
2
1
28 27 26  
25  
5
6
7
8
9
B5  
B4  
B3  
NC  
B2  
A6  
A5  
A4  
NC  
A3  
A2  
A1  
24  
23  
22  
21  
20  
19  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW), and  
Thin Very Small-Outline (DGV) Packages,  
Ceramic Chip Carriers (FK), and Ceramic  
(JT) DIPs  
10  
11  
B1  
OEAB  
12 13 14 15 16 17 18  
description  
These octal bus transceivers and registers are  
designed specifically for low-voltage (3.3-V) V  
CC  
operation, but with the capability to provide a TTL  
interface to a 5-V system environment.  
NC – No internal connection  
The ’LVTH2952 devices consist of two 8-bit back-to-back registers that store data flowing in both directions  
between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition  
of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB or CLKENBA) input is low.  
Taking the output-enable (OEAB or OEBA) input low accesses the data on either port.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
When V is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V  
through a pullup resistor;  
CC  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

中文翻译

下载PDF

与SN54LVTH2952JT相关器件

型号 品牌 获取价格 描述 数据表
SN54LVTH373 TI

获取价格

 		3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVTH373_07 TI

获取价格

 		3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVTH373_08 TI

获取价格

 		3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVTH373FK TI

获取价格

 		3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVTH373J TI

获取价格

 		3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVTH373W TI

获取价格

 		3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVTH374 TI

获取价格

 		3.3 V ABT OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS
SN54LVTH374_08 TI

获取价格

 		3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVTH374FK TI

获取价格

 		3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVTH374J TI

获取价格

 		3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

与SN54LVTH2952JT相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证