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SN54LVTH541J PDF预览

SN54LVTH541J

更新时间： 2024-11-23 23:03:07
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路输出元件信息通信管理
页数 文件大小 规格书
13页 308K
描述
3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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SN54LVTH541J 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：20
Reach Compliance Code：unknown风险等级：5.84
Is Samacsys：N其他特性：WITH DUAL OUTPUT ENABLE
系列：LVTJESD-30 代码：R-GDIP-T20
长度：24.195 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE最大电源电流（ICC）：5 mA
传播延迟（tpd）：4 ns认证状态：Not Qualified
座面最大高度：5.08 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：NO技术：BICMOS
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

SN54LVTH541J 数据手册

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SCBS682G − MARCH 1997 − REVISED OCTOBER 2003  
SN54LVTH541 . . . J OR W PACKAGE  
SN74LVTH541 . . . DB, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
)
CC  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
OE1  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
V
CC  
OE2  
Y1  
1
2
3
4
5
6
7
8
9
20  
19  
18  
Support Unregulated Battery Operation  
Down to 2.7 V  
17 Y2  
16 Y3  
15 Y4  
14 Y5  
13 Y6  
12 Y7  
11 Y8  
I
and Power-Up 3-State Support Hot  
off  
Insertion  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
D
D
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
GND 10  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
SN54LVTH541 . . . FK PACKAGE  
(TOP VIEW)  
description/ordering information  
3
2
1 20 19  
18  
These octal buffers/drivers are designed  
Y1  
Y2  
Y3  
Y4  
Y5  
A3  
A4  
A5  
A6  
A7  
4
5
6
7
8
specifically for low-voltage (3.3-V) V  
operation,  
CC  
17  
16  
15  
14  
but with the capability to provide a TTL interface  
to a 5-V system environment.  
The ’LVTH541 devices are ideal for driving bus  
lines or buffer-memory address registers. These  
devices feature inputs and outputs on opposite  
sides of the package that facilitate printed circuit  
board layout.  
9 10 11 12 13  
The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2)  
input is high, all outputs are in the high-impedance state.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
Tube  
SN74LVTH541DW  
SN74LVTH541DWR  
SN74LVTH541NSR  
SN74LVTH541DBR  
SN74LVTH541PW  
SN74LVTH541PWR  
SNJ54LVTH541J  
SOIC − DW  
LVTH541  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
LVTH541  
LXH541  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
LXH541  
Tape and reel  
Tube  
CDIP − J  
CFP − W  
LCCC - FK  
SNJ54LVTH541J  
SNJ54LVTH541W  
SNJ54LVTH541FK  
−55°C to 125°C  
Tube  
SNJ54LVTH541W  
SNJ54LVTH541FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

中文翻译

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