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SN54LVTH373_08

更新时间： 2024-11-20 05:04:55
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德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
18页 642K
描述
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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SN54LVTH373_08 数据手册

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SCBS689H − MAY 1997 − REVISED OCTOBER 2003  
SN54LVTH373 . . . J OR W PACKAGE  
SN74LVTH373 . . . DB, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
D
Support Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
3.3-V V  
)
CC  
D
D
D
D
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OLP  
CC  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
1
2
3
4
5
6
7
8
9
10  
V
CC  
= 3.3 V, T = 25°C  
A
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
LE  
Support Unregulated Battery Operation  
Down to 2.7 V  
I
and Power-Up 3-State Support Hot  
off  
Insertion  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
GND  
D
D
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
SN54LVTH373 . . . FK PACKAGE  
(TOP VIEW)  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
description/ordering information  
3
2
1 20 19  
18  
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
6Q  
6D  
4
5
6
7
8
17  
16  
15  
14  
These octal latches are designed specifically for  
low-voltage (3.3-V) V  
operation, but with the  
CC  
capability to provide a TTL interface to a  
5-V system environment.  
9 10 11 12 13  
While the latch-enable (LE) input is high, the Q  
outputs follow the data (D) inputs. When LE is  
taken low, the Q outputs are latched at the logic  
levels set up at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without need for interface or pullup components.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
Tube  
SN74LVTH373DW  
SN74LVTH373DWR  
SN74LVTH373NSR  
SN74LVTH373DBR  
SN74LVTH373PW  
SN74LVTH373PWR  
SNJ54LVTH373J  
SOIC − DW  
LVTH373  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
LVTH373  
LXH373  
−40°C to 85°C  
−55°C to 125°C  
SSOP − DB  
TSSOP − PW  
LXH373  
Tape and reel  
Tube  
CDIP − J  
CFP − W  
LCCC - FK  
SNJ54LVTH373J  
SNJ54LVTH373W  
SNJ54LVTH373FK  
Tube  
SNJ54LVTH373W  
SNJ54LVTH373FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...18

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 		3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
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 		3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
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 		3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
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