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SN54LVTH540 PDF预览

SN54LVTH540

更新时间： 2024-11-19 22:33:07
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
7页 106K
描述
3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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SN54LVTH540 数据手册

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SN54LVTH540, SN74LVTH540  
3.3-V ABT OCTAL BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCBS681E – MARCH 1997 – REVISED APRIL 1999  
SN54LVTH540 . . . J OR W PACKAGE  
SN74LVTH540 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
OE1  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
V
CC  
OE2  
Y1  
1
2
3
4
5
6
7
8
9
20  
19  
18  
I
and Power-Up 3-State Support Hot  
off  
Insertion  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
17 Y2  
16 Y3  
15 Y4  
14 Y5  
13 Y6  
12 Y7  
11 Y8  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
)
CC  
Support Unregulated Battery Operation  
Down to 2.7 V  
GND 10  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
SN54LVTH540 . . . FK PACKAGE  
(TOP VIEW)  
= 3.3 V, T = 25°C  
CC  
A
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
3
2
1 20 19  
18  
Y1  
Y2  
Y3  
Y4  
Y5  
A3  
A4  
A5  
A6  
A7  
4
5
6
7
8
17  
16  
15  
14  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Ceramic Flat (W) Package, and Ceramic (J)  
DIPs  
9 10 11 12 13  
description  
These octal buffers/drivers are designed specifically for low-voltage (3.3-V) V  
capability to provide a TTL interface to a 5-V system environment.  
operation, but with the  
CC  
The ’LVTH540 devices are ideal for driving bus lines or buffer memory address registers. These devices feature  
inputs and outputs on opposite sides of the package that facilitate printed circuit board layout.  
The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2)  
input is high, all outputs are in the high-impedance state.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
When V is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V  
through a pullup resistor;  
CC  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry  
off  
off  
disables the outputs, preventing damaging current backflow through the devices when they are powered down.  
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,  
which prevents driver conflict.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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SN54LVTH541WR TI

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 		暂无描述
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