Datasheet > SN54LVT8986HV

SN54LVT8986HV

更新时间： 2024-09-15 00:04:23

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SN54LVT8986HV 数据手册

SN54LVT8986, SN74LVT8986

3.3-V LINKING ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

www.ti.com

SCBS759D–OCTOBER 2002–REVISED MARCH 2006

FEATURES

•

Members of the Texas Instruments (TI) Family

of JTAG Scan-Support Products

•

Bypass (BYP₅–BYP₀) Forces Primary to

Configured Secondary Paths Without Use of

Linking Shadow Protocols

Extend Scan Access From Board Level to

Higher Level of System Integration

•

Connect (CON₂–CON₀) Provides Indication of

Primary-to-Secondary Paths Connections

Three IEEE Std 1149.1-Compatible

Configurable Secondary Scan Paths to One

Primary Scan Path

Secondary TAPs Can Be Configured at High

Impedance Via the OE Input to Allow an

Alternate Test Master to Take Control of the

Secondary TAPs

•

Multiple Devices Can Be Cascaded to Link 24

Secondary Scan Paths to One Primary Scan

Path

•

High-Drive Outputs (–32-mA I_OH, 64-mA I_OL

Support Backplane Interface at Primary

Outputs and High Fanout at Secondary

Outputs

)

Simple (Linking Shadow) Protocol Is Used to

Connect the Primary Test Access Port (TAP)

to Secondary TAPs. This Single Protocol Is

Used to Address and Configure the

Secondary Scan Path.

While Powered at 3.3 V, Both Primary and

Secondary TAPs Are Fully 5-V Tolerant for

Interfacing 5-V and/or 3.3-V Masters and

Targets

•

LASP (8986) and ASP (8996) Can Be

Configured on the Same Backplane Using

Similar Shadow Protocols

Package Options Include Plastic BGA (GGV)

and LQFP (PM) Packages and Ceramic Quad

Flat (HV) Packages Using 25-mil

Linking Shadow Protocols Can Occur in Any

of Test-Logic-Reset, Run-Test/Idle, Pause-DR,

Pause-IR TAP States to Provide

Center-to-Center Spacing

Board-to-Board and Built-In Self-Test

DESCRIPTION/ORDERING INFORMATION

The 'LVT8986 linking addressable scan ports (LASPs) are members of the TI family of IEEE Std 1149.1 (JTAG)

scan-support products. The scan-support product family facilitates testing of fully boundary-scannable devices.

The LASP applies linking shadow protocols through the test access port (TAP) to extend scan access to the

system level and divide scan chains at the board level.

The LASP consists of a primary TAP for interfacing to the backplane IEEE Std 1149.1 serial-bus signals (PTDI,

PTMS, PTCK, PTDO, PRTST) and three secondary TAPs for interfacing to the board-level IEEE Std 1149.1

serial-bus signals. Each secondary TAP consists of signals STDI_x, STMS_x, STCK_x, STDO_x, and STRST_x.

Conceptually, the LASP is a gateway device that can be used to connect a set of primary TAP signals to a set of

secondary TAP signals – for example, to interface backplane TAP signals to a board-level TAP. The LASP

provides all signal buffering that might be required at these two interfaces. Primary-to-secondary TAP

connections can be configured with the help of linking shadow protocol or protocol bypass (BYP₅–BYP₀) inputs.

All possible configurations are tabulated in Function Tables 1, 2, and 3.

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾

ORDERABLE PART NUMBER

SN74LVT8986GGV

TOP-SIDE MARKING

LVT8986

PBGA – GGV

–40°C to 85°C

PBGA – ZGV

LQFP – PM

CFP – HV

SN74LVT8986ZGV

LVT8986

SN74LVT8986PM

LVT8986

–55°C to 125°C

SNJ54LVT8986HV

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

On products compliant to MIL-PRF-38535, all parameters are

Instruments standard warranty. Production processing does not

tested unless otherwise noted. On all other products, production

necessarily include testing of all parameters.

processing does not necessarily include testing of all parameters.

12 3 4 5 6 7...54

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与SN54LVT8986HV相关器件

型号	品牌	获取价格	描述	数据表
SN54LVT8996	TI	获取价格	3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 JTAG TAP TRANSCE
SN54LVT8996_99	TI	获取价格	3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANS
SN54LVT8996FK	TI	获取价格	3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 JTAG TAP TRANSCE
SN54LVT8996FKR	TI	获取价格	SPECIALTY MICROPROCESSOR CIRCUIT, CQCC28, CERAMIC, LCC-28
SN54LVT8996JT	TI	获取价格	3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 JTAG TAP TRANSCE
SN54LVTH125	TI	获取价格	3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN54LVTH125_07	TI	获取价格	3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN54LVTH125_09	TI	获取价格	3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN54LVTH125_10	TI	获取价格	3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN54LVTH125FK	TI	获取价格	3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS

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