SN54LVT8996, SN74LVT8996
3.3-V 10-BIT ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS686A – APRIL 1997 – REVISED DECEMBER 1999
Members of the Texas Instruments (TI )
Simple Addressing (Shadow) Protocol Is
Received/Acknowledged on Primary TAP
Broad Family of Testability Products
Supporting IEEE Std 1149.1-1990 (JTAG)
Test Access Port (TAP) and Boundary-Scan
Architecture
10-Bit Address Space Provides for up to
1021 User-Specified Board Addresses
Bypass (BYP) Pin Forces
Primary-to-Secondary Connection Without
Use of Shadow Protocols
Extend Scan Access From Board Level to
Higher Levels of System Integration
Promote Reuse of Lower-Level
(Chip/Board) Tests in System Environment
Connect (CON) Pin Provides Indication of
Primary-to-Secondary Connection
While Powered at 3.3 V, Both the Primary
and Secondary TAPs Are Fully 5-V Tolerant
for Interfacing to 5-V and/or 3.3-V Masters
and Targets
High-Drive Outputs (–32-mA I , 64-mA I
Support Backplane Interface at Primary and
High Fanout at Secondary
)
OH
OL
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Switch-Based Architecture Allows Direct
Connect of Primary TAP to Secondary TAP
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Primary TAP Is Multidrop for Minimal Use of
Backplane Wiring Channels
– 1000-V Charged-Device Model (C101)
Shadow Protocols Can Occur in Any of
Test-Logic-Reset, Run-Test/Idle, Pause-DR,
and Pause-IR TAP States to Provide for
Board-to-Board Test and Built-In Self-Test
Package Options Include Plastic
Small-Outline (DW) and Thin Shrink
Small-Outline (PW) Packages, Ceramic
Chip Carriers (FK), and Ceramic DIPs (JT)
SN54LVT8996 . . . JT PACKAGE
SN74LVT8996 . . . DW OR PW PACKAGE
(TOP VIEW)
SN54LVT8996 . . . FK PACKAGE
(TOP VIEW)
A4
A3
A2
A1
A0
A5
A6
A7
A8
A9
V
CON
STDI
STCK
STMS
STDO
STRST
1
24
23
22
21
20
19
18
17
16
15
14
13
4
3
2
1 28 27 26
25
2
A1
A0
A8
A9
V
5
3
24
23
22
6
4
BYP
NC
7
CC
5
NC
8
BYP
GND
PTDO
PTCK
PTMS
PTDI
PTRST
6
GND
PTDO
21 CON
9
CC
7
20
19
STDI
10
8
PTCK 11
STCK
12 13 14 15 16 17 18
9
10
11
12
NC – No internal connection
description
The ’LVT8996 10-bit addressable scan ports (ASP) are members of the Texas Instruments SCOPE testability
integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate
testing of complex circuit assemblies. Unlike most SCOPE devices, the ASP is not a boundary-scannable
device, rather, it applies TI’s addressable-shadow-port technology to the IEEE Std 1149.1-1990 (JTAG) test
access port (TAP) to extend scan access beyond the board level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE and TI are trademarks of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
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