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SN54LVTH125_09

更新时间： 2024-11-25 09:17:39
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德州仪器 - TI 输出元件
页数 文件大小 规格书
19页 764K
描述
3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS

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SN54LVTH125_09 数据手册

 浏览型号SN54LVTH125_09的Datasheet PDF文件第2页浏览型号SN54LVTH125_09的Datasheet PDF文件第3页浏览型号SN54LVTH125_09的Datasheet PDF文件第4页浏览型号SN54LVTH125_09的Datasheet PDF文件第5页浏览型号SN54LVTH125_09的Datasheet PDF文件第6页浏览型号SN54LVTH125_09的Datasheet PDF文件第7页 
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SCBS703I − AUGUST 1997 − REVISED OCTOBER 2003  
D
D
D
D
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
D
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
)
CC  
Support Unregulated Battery Operation  
Down to 2.7 V  
D
D
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
A
I
and Power-Up 3-State Support Hot  
off  
Insertion  
SN74LVTH125 . . . RGY PACKAGE  
(TOP VIEW)  
SN54LVTH125 . . . FK PACKAGE  
(TOP VIEW)  
SN54LVTH125 . . . J OR W PACKAGE  
SN74LVTH125 . . . D, DB, DGV, NS,  
OR PW PACKAGE  
(TOP VIEW)  
1
14  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OE  
1A  
1Y  
2OE  
2A  
2Y  
V
CC  
4OE  
3
2
1
20 19  
18 4A  
1A  
1Y  
13 4OE  
12 4A  
1Y  
NC  
2
3
4
5
6
4
5
6
7
8
17  
16  
15  
14  
NC  
4Y  
4A  
4Y  
3OE  
3A  
3Y  
11  
10  
9
2OE  
2A  
4Y  
2OE  
NC  
3OE  
3A  
NC  
3OE  
2Y  
2A  
9 10 11 12 13  
7
8
8
GND  
NC − No internal connection  
description/ordering information  
These bus buffers are designed specifically for low-voltage (3.3-V) V  
provide a TTL interface to a 5-V system environment.  
operation, but with the capability to  
CC  
The ’LVTH125 devices feature independent line drivers with 3-state outputs. Each output is in the  
high-impedance state when the associated output-enable (OE) input is high.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
QFN − RGY  
SOIC − D  
Tape and reel  
Tube  
SN74LVTH125RGYR  
SN74LVTH125D  
LXH125  
LVTH125  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SN74LVTH125DR  
SN74LVTH125NSR  
SN74LVTH125DBR  
SN74LVTH125PW  
SN74LVTH125PWR  
SN74LVTH125DGVR  
SNJ54LVTH125J  
SOP − NS  
LVTH125  
LXH125  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
LXH125  
Tape and reel  
Tape and reel  
Tube  
TVSOP − DGV  
CDIP − J  
LXH125  
SNJ54LVTH125J  
SNJ54LVTH125W  
SNJ54LVTH125FK  
CFP − W  
Tube  
SNJ54LVTH125W  
SNJ54LVTH125FK  
−55°C to 125°C  
LCCC − FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...19

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