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SN54LVT574 PDF预览

SN54LVT574

更新时间: 2024-10-31 23:03:07
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德州仪器 - TI 触发器输出元件
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15页 468K
描述
3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

SN54LVT574 数据手册

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SN54LVT574, SN74LVT574  
3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCBS139D – MAY 1992 – REVISED JULY 1995  
SN54LVT574 . . . J OR W PACKAGE  
SN74LVT574 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static Power  
Dissipation  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
)
CC  
Support Unregulated Battery Operation  
Down to 2.7 V  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
13 7Q  
12 8Q  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
11  
GND  
CLK  
SN54LVT574 . . . FK PACKAGE  
(TOP VIEW)  
Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
Bus-Hold Data Inputs Eliminate the Need  
for External Pullup Resistors  
Support Live Insertion  
3
2
1
20 19  
18  
4
5
6
7
8
3D  
4D  
5D  
6D  
7D  
2Q  
3Q  
4Q  
5Q  
6Q  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Ceramic Flat (W) Packages, and Ceramic  
(J) DIPs  
17  
16  
15  
14  
9 10 11 12 13  
description  
These octal flip-flops are designed specifically for low-voltage (3.3-V) V  
provide a TTL interface to a 5-V system environment.  
operation, but with the capability to  
CC  
The eight flip-flops of the LVT574 are edge-triggered D-type flip-flops. On the positive transition of the clock  
(CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without need for interface or pullup components. OE does not affect the internal operations of the flip-flops.  
Old data can be retained or new data can be entered while the outputs are in the high-impedance state.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN74LVT574 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LVT574 is characterized for operation over the full military temperature range of 55°C to 125°C. The  
SN74LVT574 is characterized for operation from 40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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