Datasheet > 逻辑 > 总线驱动器/收发器> SN54LVT646JT

SN54LVT646JT

更新时间： 2024-09-12 23:03:07

品牌	Logo	应用领域
德州仪器 - TI		总线驱动器总线收发器触发器逻辑集成电路输出元件输入元件信息通信管理
页数	文件大小	规格书
10页	157K
描述
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

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SN54LVT646JT 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	DIP	包装说明：	DIP, DIP24,.3
针数：	24	Reach Compliance Code：	not_compliant
ECCN代码：	3A001.A.2.C	HTS代码：	8542.39.00.01
风险等级：	5.92	Is Samacsys：	N
其他特性：	DIRECTION CONTROL; SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED OR REAL TIME DATA	控制类型：	INDEPENDENT CONTROL
计数方向：	BIDIRECTIONAL	系列：	LVT
JESD-30 代码：	R-GDIP-T24	长度：	32.005 mm
负载电容（CL）：	50 pF	逻辑集成电路类型：	REGISTERED BUS TRANSCEIVER
最大I（ol）：	0.048 A	位数：	8
功能数量：	1	端口数量：	2
端子数量：	24	最高工作温度：	125 °C
最低工作温度：	-55 °C	输出特性：	3-STATE
输出极性：	TRUE	封装主体材料：	CERAMIC, GLASS-SEALED
封装代码：	DIP	封装等效代码：	DIP24,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	3.3 V
最大电源电流（ICC）：	14 mA	Prop。Delay @ Nom-Sup：	4.9 ns
传播延迟（tpd）：	6.6 ns	认证状态：	Not Qualified
座面最大高度：	5.08 mm	子类别：	Bus Driver/Transceivers
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	2.7 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	NO
技术：	BICMOS	温度等级：	MILITARY
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
翻译：	N/A	触发器类型：	POSITIVE EDGE
宽度：	7.62 mm	Base Number Matches：	1

SN54LVT646JT 数据手册

SN54LVT646, SN74LVT646

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS140D – MAY 1992 – REVISED JULY 1995

SN54LVT646 . . . JT OR W PACKAGE

SN74LVT646 . . . DB, DW, OR PW PACKAGE

(TOP VIEW)

State-of-the-Art Advanced BiCMOS

Technology (ABT) Design for 3.3-V

Operation and Low Static Power

Dissipation

CLKAB

SAB

DIR

Support Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V V

CLKBA

SBA

)

Support Unregulated Battery Operation

Down to 2.7 V

Typical V

< 0.8 V at V

(Output Ground Bounce)

OLP

= 3.3 V, T = 25°C

ESD Protection Exceeds 2000 V Per

MIL-STD-883C, Method 3015; Exceeds

200 V Using Machine Model

(C = 200 pF, R = 0)

GND

Latch-Up Performance Exceeds 500 mA

Per JEDEC Standard JESD-17

SN54LVT646 . . . FK PACKAGE

(TOP VIEW)

Bus-Hold Data Inputs Eliminate the Need

for External Pullup Resistors

Support Live Insertion

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), and and Thin Shrink Small-Outline

(PW) Packages, Ceramic Chip Carriers

(FK), Ceramic Flat (W) Packages, and

Ceramic (JT) DIPs

28 27 26

21 B3

description

These bus transceivers and registers are

designed specifically for low-voltage (3.3-V) V

12 13 14 15 16 17 18

operation, but with the capability to provide a TTL

interface to a 5-V system environment.

NC – No internal connection

The ’LVT646 consist of bus transceiver circuits,

D-type flip-flops, and control circuitry arranged for

multiplexed transmission of data directly from the

input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high

transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental

bus-management functions that can be performed with the ′LVT646.

Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the

transceiver mode, data present at the high-impedance port may be stored in either register or in both.

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The

direction control (DIR) determines which bus receives data when OE is low. In the isolation mode (OE high),

A data may be stored in one register and/or B data may be stored in the other register.

When an output function is disabled, the input function is still enabled and may be used to store and transmit

data. Only one of the two buses, A or B, may be driven at a time.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...10

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与SN54LVT646JT相关器件

型号	品牌	获取价格	描述	数据表
SN54LVT646W	TI	获取价格	3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54LVT652	TI	获取价格	3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54LVT760FK	TI	获取价格	LVT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, CQCC28
SN54LVT760J	TI	获取价格	LVT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, CDIP20
SN54LVT8980	TI	获取价格	EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 8-BIT GENERIC HOST INT
SN54LVT8980_06	TI	获取价格	EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST I
SN54LVT8980A	TI	获取价格	EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTER WITH 8-BIT GENERIC HOST IN
SN54LVT8980A_14	TI	获取价格	EMBEDDED TEST-BUS CONTROLLERS
SN54LVT8980AFK	TI	获取价格	EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTER WITH 8-BIT GENERIC HOST IN
SN54LVT8980AJT	TI	获取价格	EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTER WITH 8-BIT GENERIC HOST IN

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