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SN54LVT8980A_14

更新时间： 2024-11-06 02:58:51
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德州仪器 - TI /
页数 文件大小 规格书
35页 575K
描述
EMBEDDED TEST-BUS CONTROLLERS

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SN54LVT8980A_14 数据手册

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SCBS755B − APRIL 2002 − REVISED MARCH 2004  
SN54LVT8980A . . . JT PACKAGE  
SN74LVT8980A . . . DW PACKAGE  
(TOP VIEW)  
D
Members of Texas Instruments Broad  
Family of Testability Products Supporting  
IEEE Std 1149.1-1990 (JTAG) Test Access  
Port (TAP) and Boundary-Scan Architecture  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
1
STRB  
R/W  
D0  
D1  
D2  
D3  
GND  
D4  
A0  
A1  
A2  
RDY  
TDO  
D
D
D
Provide Built-In Access to IEEE Std 1149.1  
Scan-Accessible Test/Maintenance  
Facilities at Board and System Levels  
2
3
4
5
While Powered at 3.3 V, the TAP Interface Is  
Fully 5-V Tolerant for Mastering Both 5-V  
and/or 3.3-V IEEE Std 1149.1 Targets  
6
V
CC  
7
TCK  
TMS  
TRST  
TDI  
RST  
TOE  
8
Simple Interface to Low-Cost 3.3-V  
Microprocessors/Microcontrollers Via 8-Bit  
Asynchronous Read/Write Data Bus  
9
D5  
D6  
D7  
10  
11  
12  
D
D
Easy Programming Via Scan-Level  
Command Set and Smart TAP Control  
CLKIN  
Transparently Generate Protocols to  
Support Multidrop TAP Configurations  
Using TI’s Addressable Scan Port  
SN54LVT8980A . . . FK PACKAGE  
(TOP VIEW)  
D
D
Flexible TCK Generator Provides  
Programmable Division, Gated-TCK, and  
Free-Running-TCK Modes  
4
3
2
1 28 27 26  
25  
D1  
RDY  
TDO  
Discrete TAP Control Mode Supports  
Arbitrary TMS/TDI Sequences for  
Noncompliant Targets  
5
D2  
D3  
NC  
6
24  
23  
22  
21  
20  
19  
V
7
CC  
NC  
8
D
D
D
D
Programmable 32-Bit Test Cycle Counter  
Allows Virtually Unlimited Scan/Test Length  
GND  
D4  
TCK  
TMS  
TRST  
9
10  
11  
Accommodate Target Retiming (Pipeline)  
Delays of up to 15 TCK Cycles  
D5  
12 13 14 15 16 17 18  
Test Output Enable (TOE) Allows for  
External Control of TAP Signals  
High-Drive Outputs (−32-mA I , 64-mA I  
)
OH  
OL  
NC − No internal connection  
at TAP Support Backplane Interface and/or  
High Fanout  
description  
The ’LVT8980A embedded test-bus controllers (eTBCs) are members of the TI broad family of testability  
integrated circuits. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of  
complex circuit assemblies. Unlike most other devices of this family, the eTBCs are not boundary-scannable  
devices; rather, their function is to master an IEEE Std 1149.1 (JTAG) test access port (TAP) under the command  
of an embedded host microprocessor/microcontroller. Thus, the eTBCs enable the practical and effective use  
of the IEEE Std 1149.1 test-access infrastructure to support embedded/built-in test, emulation, and  
configuration/maintenance facilities at board and system levels.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...35

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与SN54LVT8980A_14相关器件

型号 品牌 获取价格 描述 数据表
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SN54LVT8980AJT TI

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 		EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTER WITH 8-BIT GENERIC HOST IN
SN54LVT8980AW TI

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 		SPECIALTY MICROPROCESSOR CIRCUIT, CQCC28, CERAMIC, LCC-28
SN54LVT8980JT TI

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 		EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 8-BIT GENERIC HOST INT
SN54LVT8986 TI

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 		3.3-V LINKING ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRAN
SN54LVT8986HV TI

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SN54LVT8996 TI

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 		3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 JTAG TAP TRANSCE
SN54LVT8996_99 TI

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 		3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANS
SN54LVT8996FK TI

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 		3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 JTAG TAP TRANSCE

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