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SN54LVT8980JT

更新时间： 2024-11-24 22:36:39
品牌 Logo 应用领域
德州仪器 - TI 总线控制器测试
页数 文件大小 规格书
34页 495K
描述
EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES

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SN54LVT8980JT 数据手册

 浏览型号SN54LVT8980JT的Datasheet PDF文件第2页浏览型号SN54LVT8980JT的Datasheet PDF文件第3页浏览型号SN54LVT8980JT的Datasheet PDF文件第4页浏览型号SN54LVT8980JT的Datasheet PDF文件第5页浏览型号SN54LVT8980JT的Datasheet PDF文件第6页浏览型号SN54LVT8980JT的Datasheet PDF文件第7页 
SN54LVT8980, SN74LVT8980  
EMBEDDED TEST-BUS CONTROLLERS  
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES  
SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997  
SN54LVT8980 . . . JT PACKAGE  
SN74LVT8980 . . . DW PACKAGE  
Members of Texas Instruments (TI) Broad  
Family of Testability Products Supporting  
IEEE Std 1149.1-1990 (JTAG) Test Access  
(TOP VIEW)  
Port (TAP) and Boundary-Scan Architecture  
STRB  
R/W  
D0  
D1  
D2  
D3  
GND  
D4  
A0  
A1  
A2  
RDY  
TDO  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
Provide Built-In Access to IEEE Std 1149.1  
Scan-Accessible Test/Maintenance  
Facilities at Board and System Levels  
2
3
4
While Powered at 3.3 V, the TAP Interface is  
Fully 5-V Tolerant for Mastering Both 5-V  
and/or 3.3-V IEEE Std 1149.1 Targets  
5
V
6
CC  
TCK  
TMS  
TRST  
TDI  
RST  
TOE  
7
8
Simple Interface to Low-Cost 3.3-V  
Microprocessors/Microcontrollers Via 8-Bit  
Asynchronous Read/Write Data Bus  
D5  
D6  
D7  
9
10  
11  
12  
Easy Programming Via Scan-Level  
Command Set and Smart TAP Control  
CLKIN  
Transparently Generate Protocols to  
Support Multidrop TAP Configurations  
Using TI’s Addressable Scan Port  
SN54LVT8980 . . . FK PACKAGE  
(TOP VIEW)  
Flexible TCK Generator Provides  
Programmable Division, Gated-TCK, and  
Free-Running-TCK Modes  
4
3
2
1 28 27 26  
25  
Discrete TAP Control Mode Supports  
Arbitrary TMS/TDI Sequences for  
Non-Compliant Targets  
D1  
D2  
RDY  
TDO  
5
6
24  
23  
22  
21  
20  
19  
D3  
V
7
CC  
Programmable 32-Bit Test Cycle Counter  
Allows Virtually Unlimited Scan/Test Length  
NC  
GND  
D4  
NC  
8
TCK  
TMS  
TRST  
9
10  
11  
Accommodate Target Retiming (Pipeline)  
Delays of Up to 15 TCK Cycles  
D5  
12 13 14 15 16 17 18  
Test Output Enable (TOE) Allows for  
External Control of TAP Signals  
High-Drive Outputs (–32-mA I , 64-mA I  
)
OH  
OL  
at TAP Support Backplane Interface and/or  
High Fanout  
NC – No internal connection  
Package Options Include Plastic  
Small-Outline (DW) Package, Ceramic Chip  
Carriers (FK), and Ceramic 300-mil DIPs (JT)  
description  
The’LVT8980embeddedtest-buscontrollers(eTBC)aremembersoftheTIbroadfamilyoftestabilityintegrated  
circuits. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex  
circuit assemblies. Unlike most other devices of this family, the eTBC is not a boundary-scannable device;  
rather, its function is to master an IEEE Std 1149.1 (JTAG) test access port (TAP) under the command of an  
embedded host microprocessor/microcontroller. Thus, the eTBC enables the practical and effective use of the  
IEEE Std 1149.1 test-access infrastructure to support embedded/built-in test, emulation, and  
configuration/maintenance facilities at board and system levels.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...34

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