SN54LV123A, SN74LV123A
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
WITH SCHMITT-TRIGGER INPUTS
SCLS393O − APRIL 1998 − REVISED OCTOBER 2005
D
D
D
D
D
D
D
2-V to 5.5-V V Operation
D
D
D
D
D
I
Supports Partial-Power-Down Mode
CC
off
Operation
Max t of 11 ns at 5 V
pd
Retriggerable for Very Long Output Pulses,
up to 100% Duty Cycle
Typical V
(Output Ground Bounce)
OLP
<0.8 V at V = 3.3 V, T = 25°C
CC
A
Overriding Clear Terminates Output Pulse
Glitch-Free Power-Up Reset on Outputs
Typical V
(Output V Undershoot)
OHV
OH
>2.3 V at V = 3.3 V, T = 25°C
CC
A
Support Mixed-Mode Voltage Operation on
All Ports
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Schmitt-Trigger Circuitry on A, B, and CLR
Inputs for Slow Input Transition Rates
D
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Edge Triggered From Active-High or
Active-Low Gated Logic Inputs
− 1000-V Charged-Device Model (C101)
SN74LV123A . . . RGY PACKAGE
(TOP VIEW)
SN54LV123A . . . FK PACKAGE
(TOP VIEW)
SN54LV123A . . . J OR W PACKAGE
SN74LV123A . . . D, DB, DGV, NS,
OR PW PACKAGE
(TOP VIEW)
1
16
1A
1B
1CLR
1Q
VCC
1
2
3
4
5
6
7
8
16
15
14
13
15
14
13
12
11
10
1B
1CLR
1Q
2Q
2Cext
2
3
4
5
6
7
1Rext/Cext
1Cext
1Q
2Q
2CLR
2B
1Rext/Cext
1Cext
1Q
3
2
1 20 19
18
1Cext
1Q
NC
1CLR
1Q
NC
2Q
2Cext
4
5
6
7
8
17
16
2Q
12 2Q
11
10
9
2Cext
2Rext/Cext
GND
2CLR
2B
2A
15 2Q
14
9 10 11 12 13
2Rext/Cext
2CLR
8
9
NC − No internal connection
description/ordering information
The ’LV123A devices are dual retriggerable monostable multivibrators designed for 2-V to 5.5-V V operation.
CC
These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method,
the A input is low and the B input goes high. In the second method, the B input is high and the A input goes low.
In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmable by selecting external resistance and capacitance values. The
external timing capacitor must be connected between C and R /C (positive) and an external resistor
ext
ext ext
connected between R /C
and V . To obtain variable pulse durations, connect an external variable
ext ext
CC
resistance between R /C and V . The output pulse duration also can be reduced by taking CLR low.
ext ext
CC
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition
rates with jitter-free triggering at the outputs.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or
high-level-active (B) input. Pulse duration can be reduced by taking CLR low. The input/output timing diagram
illustrates pulse control by retriggering the inputs and early clearing.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2005, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
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