SN54LV125A

更新时间： 2024-11-01 22:37:15

品牌	Logo	应用领域
德州仪器 - TI		输出元件
页数	文件大小	规格书
17页	512K
描述
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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中文翻译

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数据手册

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SN54LV125A 数据手册

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SCES124L − DECEMBER 1997 − REVISED APRIL 2005

2-V to 5.5-V V

Operation

Supports Partial-Power-Down Mode

off

Operation

Max t of 6 ns at 5 V

Latch-Up Performance Exceeds 250 mA Per

JESD 17

Typical V

<0.8 V at V

(Output Ground Bounce)

OLP

= 3.3 V, T = 25°C

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

Typical V

>2.3 V at V

(Output V

Undershoot)

OHV

= 3.3 V, T = 25°C

Support Mixed-Mode Voltage Operation on

All Ports

− 1000-V Charged-Device Model (C101)

SN54LV125A . . . J OR W PACKAGE

SN74LV125A . . . D, DB, DGV, N, NS,

OR PW PACKAGE

SN74LV125A . . . RGY PACKAGE

(TOP VIEW)

SN54LV125A . . . FK PACKAGE

(TOP VIEW)

20 19

1OE

13 4OE

12 4A

2OE

15 NC

9 10 11 12 13

3OE

GND

NC − No internal connection

description/ordering information

The ‘LV125A quadruple bus buffer gates are designed for 2-V to 5.5-V V

operation.

These devices feature independent line drivers with 3-state outputs. Each output is disabled when the

associated output-enable (OE) input is high.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

PDIP − N

Tube of 25

SN74LV125AN

LV125A

QFN − RGY

Reel of 1000

Tube of 50

SN74LV125ARGYR

SN74LV125AD

SOIC − D

LV125A

Reel of 2500

Reel of 2000

Tube of 90

SN74LV125ADR

SN74LV125ANSR

SN74LV125ADBR

SN74LV125APW

SN74LV125APWR

SN74LV125APWT

SN74LV125ADGVR

SNJ54LV125AJ

SOP − NS

74LV125A

LV125A

−40°C to 85°C

SSOP − DB

Reel of 2000

Reel of 250

Reel of 2000

Tube of 25

TSSOP − PW

LV125A

TVSOP − DGV

CDIP − J

LV125A

SNJ54LV125AJ

SNJ54LV125AW

SNJ54LV125AFK

−55°C to 125°C

CFP − W

Tube of 150

Tube of 55

SNJ54LV125AW

SNJ54LV125AFK

LCCC − FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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ꢞ ꢪꢤ ꢡ ꢝ ꢨꢝ ꢡ ꢦ ꢛ ꢝꢠ ꢥꢞ ꢪꢤ ꢩ ꢛ ꢜꢤ ꢛ ꢤ ꢩꢣ ꢞ ꢠꢨ ꢔꢤꢮ ꢦꢞ ꢖꢥꢞ ꢛꢩ ꢢꢣ ꢤꢥꢛ ꢞ ꢞꢛ ꢦꢥ ꢟꢦꢩ ꢟ ꢯ ꢦꢩ ꢩ ꢦ ꢥꢛꢰꢭ

ꢏꢩ ꢠ ꢟꢢꢡ ꢛ ꢝ ꢠꢥ ꢪꢩ ꢠ ꢡ ꢤ ꢞ ꢞ ꢝꢥ ꢱ ꢟ ꢠꢤꢞ ꢥꢠꢛ ꢥꢤ ꢡꢤ ꢞꢞ ꢦꢩ ꢝꢬ ꢰ ꢝꢥꢡ ꢬꢢꢟ ꢤ ꢛꢤ ꢞꢛ ꢝꢥꢱ ꢠꢨ ꢦꢬ ꢬ

ꢪꢦ ꢩ ꢦ ꢣ ꢤ ꢛ ꢤ ꢩ ꢞ ꢭ

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...17

中文翻译

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与SN54LV125A相关器件

型号	品牌	获取价格	描述	数据表
SN54LV125A_07	TI	获取价格	QUADRUPLE BUS BUFFER GATES
SN54LV125A_10	TI	获取价格	QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN54LV125AFK	TI	获取价格	QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN54LV125AJ	TI	获取价格	QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN54LV125AW	TI	获取价格	QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN54LV126A	TI	获取价格	QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN54LV126AD	TI	获取价格	LV/LV-A/LVX/H SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14
SN54LV126ADBLE	TI	获取价格	LV/LV-A/LVX/H SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14
SN54LV126ADR	TI	获取价格	暂无描述
SN54LV126AFK	TI	获取价格	QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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