ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢉꢊ ꢀꢁꢋ ꢃꢄꢅ ꢆꢇ ꢈꢉ
ꢌ ꢍꢉꢎꢏ ꢍꢐꢄ ꢑ ꢐꢒ ꢀꢓ ꢔ ꢓꢅꢑ ꢕꢁꢉꢁ ꢎ ꢖ ꢉꢔꢑ ꢀ
ꢗ ꢓꢔ ꢘ ꢀꢙ ꢘꢚꢓ ꢔꢔꢕꢔ ꢏꢓꢖ ꢖ ꢑ ꢏ ꢓ ꢁꢐ ꢍ ꢔꢀ
SCLS394H − APRIL 1998 − REVISED APRIL 2005
SN54LV132A . . . J OR W PACKAGE
SN74LV132A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
D
D
D
2-V to 5.5-V V
Operation
CC
Max t of 9 ns at 5 V
pd
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
1A
1B
V
CC
13 4B
1
2
3
4
5
6
7
14
= 3.3 V, T = 25°C
A
Typical V
>2.3 V at V
(Output V
Undershoot)
OHV
CC
OH
12
11
10
9
1Y
4A
4Y
3B
3A
3Y
= 3.3 V, T = 25°C
A
2A
Support Mixed-Mode Voltage Operation on
All Ports
2B
2Y
Latch-Up Performance Exceeds 250 mA Per
JESD 17
8
GND
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN54LV132A . . . FK PACKAGE
(TOP VIEW)
− 1000-V Charged-Device Model (C101)
description/ordering information
3
2
1 20 19
18
4A
17 NC
1Y
NC
2A
4
5
6
7
8
The
positive-NAND gates designed for 2-V to 5.5-V
operation.
’LV132A
devices
are
quadruple
16
4Y
NC
3B
V
15
14
NC
2B
CC
The ’LV132A devices perform the Boolean
function Y = A • B or Y = A + B in positive logic.
9 10 11 12 13
Each circuit functions as a NAND gate, but
because of the Schmitt action, it has different input
threshold levels for positive- and negative-going
signals.
NC − No internal connection
These circuits are temperature compensated and
can be triggered from the slowest of input ramps
and still give clean jitter-free output signals.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube of 25
SN74LV132AD
SOIC − D
LV132A
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
SN74LV132ADR
SN74LV132ANSR
SN74LV132ADBR
SN74LV132APW
SN74LV132APWR
SN74LV132APWT
SN74LV132ADGVR
SNJ54LV132AJ
SOP − NS
74LV132A
LV132A
SSOP − DB
−40°C to 85°C
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
TSSOP − PW
LV132A
TVSOP − DGV
CDIP − J
LV132A
SNJ54LV132AJ
SNJ54LV132AW
SNJ54LV132AFK
−55°C to 125°C
CFP − W
Tube of 150
Tube of 55
SNJ54LV132AW
SNJ54LV132AFK
LCCC - FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
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