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SI5369C-C-GQ PDF预览

SI5369C-C-GQ

更新时间: 2024-11-07 19:52:35
品牌 Logo 应用领域
芯科 - SILICON 时钟外围集成电路晶体
页数 文件大小 规格书
84页 1447K
描述
Processor Specific Clock Generator, 346MHz, CMOS, PQFP100, TQFP-100

SI5369C-C-GQ 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:QFP包装说明:HTFQFP, TQFP100,.63SQ
针数:100Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.72其他特性:CAN ALSO OPERATE AT 2.5V AND 3.3V SUPPLY
JESD-30 代码:S-PQFP-G100长度:14 mm
端子数量:100最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:346 MHz
封装主体材料:PLASTIC/EPOXY封装代码:HTFQFP
封装等效代码:TQFP100,.63SQ封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.8/3.3 V主时钟/晶体标称频率:710 MHz
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Clock Generators最大压摆率:435 mA
最大供电电压:1.89 V最小供电电压:1.71 V
标称供电电压:1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

SI5369C-C-GQ 数据手册

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Si5369  
ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER  
ATTENUATOR  
Features  
Generates any frequency from 2 kHz Five clock outputs with selectable  
to 945 MHz and select frequencies to  
1.4 GHz from an input frequency of  
2 kHz to 710 MHz  
Ultra-low jitter clock outputs with jitter  
generation as low as 300 fs rms  
(12 kHz–20 MHz)  
Integrated loop filter with selectable  
loop bandwidth (4 Hz to 525 Hz)  
Meets OC-192 GR-253-CORE jitter  
specifications  
Four clock inputs with manual or  
automatically controlled hitless  
switching and phase build-out  
Supports holdover and freerun  
modes of operation  
signal format (LVPECL, LVDS, CML,  
CMOS)  
Support for ITU G.709 and custom  
FEC ratios (253/226, 239/237,  
255/238, 255/237, 255/236)  
LOL, LOS, FOS alarm outputs  
Digitally-controlled output phase  
adjust  
I2C or SPI programmable settings  
On-chip voltage regulator for 1.8 V  
±5%, 2.5 V ±10%, or 3.3 V ±10%  
operation  
Ordering Information:  
See page 78.  
Small size: 14 x 14 mm 100-pin  
TQFP  
Pb-free, RoHS compliant  
SONET frame sync switching and  
regeneration  
Applications  
SONET/SDH OC-48/STM-16/OC-  
192/STM-64 line cards  
OTN/WDM Muxponder, MSPP,  
ROADM line cards  
GbE/10GbE, 1/2/4/8/10G FC line cards SONET/SDH + PDH clock  
synthesis  
ITU G.709 and custom FEC line cards  
Wireless repeaters/wireless backhaul  
Data converter clocking  
Test and measurement  
Synchronous Ethernet  
Broadcast video  
Description  
The Si5369 is a jitter-attenuating precision clock multiplier for applications  
requiring sub 1 ps rms jitter performance. The Si5369 accepts four clock inputs  
ranging from 2 kHz to 710 MHz and generates five clock outputs ranging from  
2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides  
virtually any frequency translation combination across this operating range. The  
outputs are divided down separately from a common source. The Si5369 input  
clock frequency and clock multiplication ratio are programmable through an I2C or  
SPI interface. The Si5369 is based on Silicon Laboratories' third-generation  
DSPLL® technology, which provides any-frequency synthesis and jitter  
attenuation in a highly integrated PLL solution that eliminates the need for  
external VCXO and loop filter components. The DSPLL loop bandwidth is digitally  
programmable, providing jitter performance optimization at the application level.  
Operating from a single 1.8, 2.5 ,or 3.3 V supply, the Si5369 is ideal for providing  
clock multiplication and jitter attenuation in high performance timing applications.  
Rev. 1.0 1/13  
Copyright © 2013 by Silicon Laboratories  
Si5369  

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