Datasheet > Si5376-EVB

Si5376-EVB

更新时间： 2024-09-18 01:09:51

品牌	Logo	应用领域
芯科 - SILICON		衰减器
页数	文件大小	规格书
66页	342K
描述
4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

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Si5376-EVB 数据手册

Si5376

4-PLL ANY-FREQUENCY PRECISION CLOCK

MULTIPLIER/JITTER ATTENUATOR

Features



Highly-integrated, 4 PLL clock

multiplier/jitter attenuator

Four independent DSPLLs support

any-frequency synthesis and jitter

attenuation



Supports all ITU G.709 and any

custom FEC ratios (239/237,

255/238, 255/237, 255/236, 253/226)

Integrated loop filter with

programmable bandwidth

Simultaneous free-run and

synchronous operation

Automatic/manual hitless input clock

switching

Selectable output clock signal format

(LVPECL, LVDS, CML, CMOS)

LOL and interrupt alarm outputs

I²C programmable

Single 1.8 V ±5% or 2.5 V ±10%

operation with high PSRR on-chip

voltage regulator



8 inputs/8 outputs

Each DSPLL can generate any

frequency from 2 kHz to 808 MHz

from a 2 kHz to 710 MHz input

350 fs rms (12 kHz– 20 MHz) and

410 fs rms (50 kHz–80 MHz)

typical

Meets ITU-T G.8251 and Telcordia

GR-253-CORE OC-192 jitter

specifications

Programmable loop bandwidth:

60 Hz to 8 kHz

Faster lock acquisition compared to

the Si5374: <1.2 s



Ordering Information:

See page 61.



10x10 mm PBGA

For a very low-loop BW version, see

the Si5374

Applications



High-density, any-port, any-protocol,  1/2/4/8/10G Fibre Channel

any-frequency line cards

ITU-T G.709 OTN custom FEC

10/40/100G



GbE/10 GbE Synchronous Ethernet

Carrier Ethernet, multi-service

switches and routers

MSPP, ROADM, P-OTS,

muxponders



OC-48/192, STM-16/64



Description

The Si5376 is a highly-integrated, 4-PLL, jitter-attenuating precision clock

multiplier for applications requiring sub-1 ps jitter performance. Each of the

DSPLL^®clock multiplier engines accepts two input clocks ranging from 2 kHz to

710 MHz and generates two independent synchronous output clocks ranging

from 2 kHz to 808 MHz. The device provides virtually any frequency translation

combination across this operating range. For asynchronous, free-running clock

generation applications, the Si5376’s reference oscillator can be used as a clock

source for any of the four DSPLLs. The Si5376 input clock frequency and clock

multiplication ratio are programmable through an I²C interface. The Si5376 is

based on Silicon Laboratories’ third-generation DSPLL^®technology, which

provides any-frequency synthesis and jitter attenuation in a highly-integrated

PLL solution that eliminates the need for external VCXO and loop filter

components. Each DSPLL loop bandwidth is digitally-programmable, providing

jitter performance optimization at the application level. The device operates from

a single 1.8 or 2.5 V supply with on-chip voltage regulators with excellent PSRR.

The Si5376 is ideal for providing clock multiplication and jitter attenuation in

high-port-count optical line cards requiring independent timing domains.

Rev. 1.0 9/12

Si5376

12 3 4 5 6 7...66

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与Si5376-EVB相关器件

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SI5380-D	SILICON	获取价格	Ultra-Low Phase Noise, 12-output JESD204B Clock Generator
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SI5380-EVB	SILICON	获取价格	Ultra-Low Phase Noise, 12-output JESD204B Clock Generator
SI5381	SILICON	获取价格	Multi-DSPLL Wireless Jitter Attenuating Clocks
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