Datasheet > Si5382A-E-GM

Si5382A-E-GM

更新时间： 2024-11-08 01:00:31

品牌	Logo	应用领域
芯科 - SILICON		无线
页数	文件大小	规格书
51页	818K
描述
Multi-DSPLL Wireless Jitter Attenuating Clocks

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Si5382A-E-GM 数据手册

Si5381/82 Data Sheet

Multi-DSPLL Wireless Jitter Attenuating Clocks

KEY FEATURES

The Si5381/82 is a wireless multi-PLL, jitter-attenuating clock that leverages Silicon

Labs’ latest fourth-generation DSPLL technology to address the form factor, power, and

performance requirements demanded by radio area network equipment, such as small

cells, baseband units, and distributed antenna systems (DAS). The Si538x is the indus-

try’s first multi-PLL wireless clock generator family capable of replacing discrete, high-

performance, VCXO-based clocks with a fully integrated CMOS IC solution. The

Si5381/82 features a multi-PLL architecture that supports independent timing paths for

JESD wireless clocks with less than 85 fs typical phase jitter as well as Ethernet and oth-

er low-jitter, general-purpose clocks. DSPLL technology also supports free-run and hold-

over operation as well as automatic and hitless input clock switching. This unparalleled

integration reduces power and size without compromising the stringent performance and

reliability demanded in wireless applications.

• Supports simultaneous wireless and

general-purpose clocking in a single

device

• Jitter performance: 85 fs RMS typ (12

kHz–20 MHz)

• Input frequency range:

• Differential: 8 kHz – 750 MHz

• LVCMOS: 8 kHz – 250 MHz

• Output frequency range:

• JESD204B: 480 kHz - 2.94912 GHz

• Differential: 1 Hz – 712.5 MHz

• LVCMOS: 480 kHz – 250 MHz

Applications

• Pico cells, small cells

• Mobile backhaul

• Multiservice Distributed Access Systems (MDAS)

Si5381/82

Integrated XO Circuit

OSC

÷INT

OUT0A

÷INT

OUT0

OUT1

OUT2

DSPLL

IN0

IN1

IN2

IN3

÷INT

DSPLL

÷INT

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

OUT9A

DSPLL

Si5381

Si5382

NVM

I²C/SPI

Control/

Status

silabs.com | Building a more connected world.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Preliminary Rev. 0.9

12 3 4 5 6 7...51

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